From dd7a2a25057d8adef591cd4373c4e12c776c5b11 Mon Sep 17 00:00:00 2001 From: Cai YiWei Date: Fri, 3 Dec 2021 17:38:05 +0800 Subject: [PATCH] media: rockchip: isp: raw data dma read/write default to burst16*4 Change-Id: I4814dacdc61f824c87dcf64caa6ff9320406800f Signed-off-by: Cai YiWei --- drivers/media/platform/rockchip/isp/hw.c | 12 ++++++++++ .../media/platform/rockchip/isp/regs_v3x.h | 22 +++++++++++++++++++ 2 files changed, 34 insertions(+) diff --git a/drivers/media/platform/rockchip/isp/hw.c b/drivers/media/platform/rockchip/isp/hw.c index 899bee986397..8801dc438b64 100644 --- a/drivers/media/platform/rockchip/isp/hw.c +++ b/drivers/media/platform/rockchip/isp/hw.c @@ -758,6 +758,18 @@ static int enable_sys_clk(struct rkisp_hw_dev *dev) writel(0, dev->base_addr + CIF_ISP_CSI0_MASK1); writel(0, dev->base_addr + CIF_ISP_CSI0_MASK2); writel(0, dev->base_addr + CIF_ISP_CSI0_MASK3); + } else if (dev->isp_ver == ISP_V30) { + writel(ISP3X_RAWX_RD_BURST_LEN16 | + ISP3X_RAWX_WR_BURST_LEN16 | + ISP3X_RD_RAWX_GROUP_MODE_X4 | + ISP3X_WR_RAWX_GROUP_MODE_X4, + dev->base_addr + ISP3X_MI_RD_CTRL2); + if (dev->is_unite) + writel(ISP3X_RAWX_RD_BURST_LEN16 | + ISP3X_RAWX_WR_BURST_LEN16 | + ISP3X_RD_RAWX_GROUP_MODE_X4 | + ISP3X_WR_RAWX_GROUP_MODE_X4, + dev->base_next_addr + ISP3X_MI_RD_CTRL2); } return 0; diff --git a/drivers/media/platform/rockchip/isp/regs_v3x.h b/drivers/media/platform/rockchip/isp/regs_v3x.h index 917ddbc1bb94..31b881684380 100644 --- a/drivers/media/platform/rockchip/isp/regs_v3x.h +++ b/drivers/media/platform/rockchip/isp/regs_v3x.h @@ -1684,6 +1684,28 @@ #define ISP3X_DBR_ST_MODE BIT(30) #define ISP3X_DBR_ST BIT(31) +/* MI_RD_CTRL2 */ +#define ISP3X_RAWX_RD_BURST_LEN_MASK GENMASK(23, 22) +#define ISP3X_RAWX_WR_BURST_LEN_MASK GENMASK(21, 20) +#define ISP3X_RD_RAWX_GROUP_MODE_MASK GENMASK(19, 18) +#define ISP3X_WR_RAWX_GROUP_MODE_MASK GENMASK(17, 16) +#define ISP3X_RAWX_RD_BURST_LEN4 0 +#define ISP3X_RAWX_RD_BURST_LEN8 BIT(22) +#define ISP3X_RAWX_RD_BURST_LEN16 BIT(23) +#define ISP3X_RAWX_RD_BURST_LEN2 (0x3 << 22) +#define ISP3X_RAWX_WR_BURST_LEN4 0 +#define ISP3X_RAWX_WR_BURST_LEN8 BIT(20) +#define ISP3X_RAWX_WR_BURST_LEN16 BIT(21) +#define ISP3X_RAWX_WR_BURST_LEN2 (0x3 << 20) +#define ISP3X_RD_RAWX_GROUP_MODE_X4 0 +#define ISP3X_RD_RAWX_GROUP_MODE_X3 BIT(18) +#define ISP3X_RD_RAWX_GROUP_MODE_X2 BIT(19) +#define ISP3X_RD_RAWX_GROUP_MODE_X1 (0x3 << 18) +#define ISP3X_WR_RAWX_GROUP_MODE_X4 0 +#define ISP3X_WR_RAWX_GROUP_MODE_X3 BIT(16) +#define ISP3X_WR_RAWX_GROUP_MODE_X2 BIT(17) +#define ISP3X_WR_RAWX_GROUP_MODE_X1 (0x3 << 16) + /* BP_WR_CTRL */ #define ISP3X_BP_ENABLE BIT(0) #define ISP3X_BP_AUTO_UPD BIT(1)