From dde2f927c2acf175635cdb420ed7930c18c508ba Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Mon, 22 Nov 2021 09:58:41 +0800 Subject: [PATCH] clk: rockchip: rk3588: support npll/aupll/v0pll power down by auto Signed-off-by: Elaine Zhang Change-Id: Ida2f113f6989eb9db9d97522514299d4660bbb69 --- drivers/clk/rockchip/clk-pll.c | 1 + drivers/clk/rockchip/clk-rk3588.c | 12 ++++++------ 2 files changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c index 3650ab47f80e..92fe99b4bdf4 100644 --- a/drivers/clk/rockchip/clk-pll.c +++ b/drivers/clk/rockchip/clk-pll.c @@ -1674,6 +1674,7 @@ struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx, init.ops = &rockchip_rk3588_pll_clk_norate_ops; else init.ops = &rockchip_rk3588_pll_clk_ops; + init.flags = flags; break; default: pr_warn("%s: Unknown pll type for pll clk %s\n", diff --git a/drivers/clk/rockchip/clk-rk3588.c b/drivers/clk/rockchip/clk-rk3588.c index bb8b6e6a2e91..0fbbcc9594bc 100644 --- a/drivers/clk/rockchip/clk-rk3588.c +++ b/drivers/clk/rockchip/clk-rk3588.c @@ -637,13 +637,13 @@ static struct rockchip_clk_branch rk3588_hdmirx_aud_fracmux __initdata = static struct rockchip_pll_clock rk3588_pll_clks[] __initdata = { [b0pll] = PLL(pll_rk3588_core, PLL_B0PLL, "b0pll", mux_pll_p, - 0, RK3588_B0_PLL_CON(0), + CLK_IGNORE_UNUSED, RK3588_B0_PLL_CON(0), RK3588_BIGCORE0_CLKSEL_CON(0), 6, 15, 0, rk3588_pll_rates), [b1pll] = PLL(pll_rk3588_core, PLL_B1PLL, "b1pll", mux_pll_p, - 0, RK3588_B1_PLL_CON(8), + CLK_IGNORE_UNUSED, RK3588_B1_PLL_CON(8), RK3588_BIGCORE1_CLKSEL_CON(0), 6, 15, 0, rk3588_pll_rates), [lpll] = PLL(pll_rk3588_core, PLL_LPLL, "lpll", mux_pll_p, - 0, RK3588_LPLL_CON(16), + CLK_IGNORE_UNUSED, RK3588_LPLL_CON(16), RK3588_DSU_CLKSEL_CON(5), 14, 15, 0, rk3588_pll_rates), [v0pll] = PLL(pll_rk3588, PLL_V0PLL, "v0pll", mux_pll_p, 0, RK3588_PLL_CON(88), @@ -652,16 +652,16 @@ static struct rockchip_pll_clock rk3588_pll_clks[] __initdata = { 0, RK3588_PLL_CON(96), RK3588_MODE_CON0, 6, 15, 0, rk3588_pll_rates), [cpll] = PLL(pll_rk3588, PLL_CPLL, "cpll", mux_pll_p, - 0, RK3588_PLL_CON(104), + CLK_IGNORE_UNUSED, RK3588_PLL_CON(104), RK3588_MODE_CON0, 8, 15, 0, rk3588_pll_rates), [gpll] = PLL(pll_rk3588, PLL_GPLL, "gpll", mux_pll_p, - 0, RK3588_PLL_CON(112), + CLK_IGNORE_UNUSED, RK3588_PLL_CON(112), RK3588_MODE_CON0, 2, 15, 0, rk3588_pll_rates), [npll] = PLL(pll_rk3588, PLL_NPLL, "npll", mux_pll_p, 0, RK3588_PLL_CON(120), RK3588_MODE_CON0, 0, 15, 0, rk3588_pll_rates), [ppll] = PLL(pll_rk3588_core, PLL_PPLL, "ppll", mux_pll_p, - 0, RK3588_PMU_PLL_CON(128), + CLK_IGNORE_UNUSED, RK3588_PMU_PLL_CON(128), RK3588_MODE_CON0, 10, 15, 0, rk3588_pll_rates), };