From ddea4b4025d5b2eae83fb96f8ea8ca4baf9e2b6d Mon Sep 17 00:00:00 2001 From: Finley Xiao Date: Thu, 9 Feb 2023 13:03:32 +0800 Subject: [PATCH] clk: rockchip: rk3562: change pll to slow mode before power down Signed-off-by: Finley Xiao Change-Id: I7ee6d2478bc012bf70ca061738534ed57d1612f0 --- drivers/clk/rockchip/clk-pll.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c index b076568cb377..15e41d50f107 100644 --- a/drivers/clk/rockchip/clk-pll.c +++ b/drivers/clk/rockchip/clk-pll.c @@ -647,17 +647,25 @@ static int rockchip_rk3036_pll_set_rate(struct clk_hw *hw, unsigned long drate, static int rockchip_rk3036_pll_enable(struct clk_hw *hw) { struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); + const struct clk_ops *pll_mux_ops = pll->pll_mux_ops; + struct clk_mux *pll_mux = &pll->pll_mux; writel(HIWORD_UPDATE(0, RK3036_PLLCON1_PWRDOWN, 0), pll->reg_base + RK3036_PLLCON(1)); rockchip_rk3036_pll_wait_lock(pll); + pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM); + return 0; } static void rockchip_rk3036_pll_disable(struct clk_hw *hw) { struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); + const struct clk_ops *pll_mux_ops = pll->pll_mux_ops; + struct clk_mux *pll_mux = &pll->pll_mux; + + pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW); writel(HIWORD_UPDATE(RK3036_PLLCON1_PWRDOWN, RK3036_PLLCON1_PWRDOWN, 0),