From de7d060208fa7e47b6d828f8d6da31729688dbe5 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Tue, 19 Apr 2022 15:27:37 +0800 Subject: [PATCH] clk: rockchip: rk3588: add PLL 1.1G parameter 1.1G may used for PPLL. Signed-off-by: Kever Yang Change-Id: I77b539ca94a5a51efa34ad2ea4b355b27b21ed0b --- drivers/clk/rockchip/clk-rk3588.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/rockchip/clk-rk3588.c b/drivers/clk/rockchip/clk-rk3588.c index 557f09fe49b1..d095f6b2991c 100644 --- a/drivers/clk/rockchip/clk-rk3588.c +++ b/drivers/clk/rockchip/clk-rk3588.c @@ -75,6 +75,7 @@ static struct rockchip_pll_rate_table rk3588_pll_rates[] = { RK3588_PLL_RATE(1320000000, 2, 220, 1, 0), RK3588_PLL_RATE(1200000000, 2, 200, 1, 0), RK3588_PLL_RATE(1188000000, 2, 198, 1, 0), + RK3588_PLL_RATE(1100000000, 3, 550, 2, 0), RK3588_PLL_RATE(1008000000, 2, 336, 2, 0), RK3588_PLL_RATE(1000000000, 3, 500, 2, 0), RK3588_PLL_RATE(983040000, 4, 655, 2, 23592),