diff --git a/drivers/video/rockchip/mpp/mpp_rkvenc2.c b/drivers/video/rockchip/mpp/mpp_rkvenc2.c
index eaf02298bb5c..4264a38629cb 100644
--- a/drivers/video/rockchip/mpp/mpp_rkvenc2.c
+++ b/drivers/video/rockchip/mpp/mpp_rkvenc2.c
@@ -56,10 +56,12 @@ enum RKVENC_FORMAT_TYPE {
 	RKVENC_FMT_BASE		= 0x0000,
 	RKVENC_FMT_H264E	= RKVENC_FMT_BASE + 0,
 	RKVENC_FMT_H265E	= RKVENC_FMT_BASE + 1,
+	RKVENC_FMT_JPEGE	= RKVENC_FMT_BASE + 2,
 
 	RKVENC_FMT_OSD_BASE	= 0x1000,
 	RKVENC_FMT_H264E_OSD	= RKVENC_FMT_OSD_BASE + 0,
 	RKVENC_FMT_H265E_OSD	= RKVENC_FMT_OSD_BASE + 1,
+	RKVENC_FMT_JPEGE_OSD	= RKVENC_FMT_OSD_BASE + 2,
 	RKVENC_FMT_BUTT,
 };
 
@@ -358,6 +360,75 @@ static struct rkvenc_hw_info rkvenc_v2_hw_info = {
 	.err_mask = 0x03f0,
 };
 
+static struct rkvenc_hw_info rkvenc_540c_hw_info = {
+	.hw = {
+		.reg_num = 254,
+		.reg_id = 0,
+		.reg_en = 4,
+		.reg_start = 160,
+		.reg_end = 253,
+	},
+	.reg_class = RKVENC_CLASS_BUTT,
+	.reg_msg[RKVENC_CLASS_BASE] = {
+		.base_s = 0x0000,
+		.base_e = 0x0120,
+	},
+	.reg_msg[RKVENC_CLASS_PIC] = {
+		.base_s = 0x0270,
+		.base_e = 0x0480,
+	},
+	.reg_msg[RKVENC_CLASS_RC] = {
+		.base_s = 0x1000,
+		.base_e = 0x110c,
+	},
+	.reg_msg[RKVENC_CLASS_PAR] = {
+		.base_s = 0x1700,
+		.base_e = 0x19cc,
+	},
+	.reg_msg[RKVENC_CLASS_SQI] = {
+		.base_s = 0x2000,
+		.base_e = 0x20fc,
+	},
+	.reg_msg[RKVENC_CLASS_SCL] = {
+		.base_s = 0x21e0,
+		.base_e = 0x2dfc,
+	},
+	.reg_msg[RKVENC_CLASS_OSD] = {
+		.base_s = 0x3000,
+		.base_e = 0x326c,
+	},
+	.reg_msg[RKVENC_CLASS_ST] = {
+		.base_s = 0x4000,
+		.base_e = 0x424c,
+	},
+	.reg_msg[RKVENC_CLASS_DEBUG] = {
+		.base_s = 0x5000,
+		.base_e = 0x5354,
+	},
+	.fd_class = RKVENC_CLASS_FD_BUTT,
+	.fd_reg[RKVENC_CLASS_FD_BASE] = {
+		.class = RKVENC_CLASS_PIC,
+		.base_fmt = RKVENC_FMT_BASE,
+	},
+	.fd_reg[RKVENC_CLASS_FD_OSD] = {
+		.class = RKVENC_CLASS_OSD,
+		.base_fmt = RKVENC_FMT_OSD_BASE,
+	},
+	.fmt_reg = {
+		.class = RKVENC_CLASS_PIC,
+		.base = 0x0300,
+		.bitpos = 0,
+		.bitlen = 2,
+	},
+	.enc_start_base = 0x0010,
+	.enc_clr_base = 0x0014,
+	.int_en_base = 0x0020,
+	.int_mask_base = 0x0024,
+	.int_clr_base = 0x0028,
+	.int_sta_base = 0x002c,
+	.enc_wdg_base = 0x0038,
+	.err_mask = 0x27d0,
+};
 /*
  * file handle translate information for v2
  */
@@ -381,6 +452,41 @@ static const u16 trans_tbl_h265e_v2_osd[] = {
 	20, 21, 22, 23, 24, 25, 26, 27,
 };
 
+/*
+ * file handle translate information for 540c
+ */
+static const u16 trans_tbl_h264e_540c[] = {
+	4, 5, 6, 7, 8, 9, 10, 11, 12, 13,
+	14, 15, 16, 17, 18, 19, 20, 21, 22, 23,
+	// /* renc and ref wrap */
+	// 24, 25, 26, 27,
+};
+
+static const u16 trans_tbl_h264e_540c_osd[] = {
+	3, 4, 12, 13, 21, 22, 30, 31,
+	39, 40, 48, 49, 57, 58, 66, 67,
+};
+
+static const u16 trans_tbl_h265e_540c[] = {
+	4, 5, 6, 7, 8, 9, 10, 11, 12, 13,
+	14, 15, 16, 17, 18, 19, 20, 21, 22, 23
+};
+
+static const u16 trans_tbl_h265e_540c_osd[] = {
+	3, 4, 12, 13, 21, 22, 30, 31,
+	39, 40, 48, 49, 57, 58, 66, 67,
+};
+
+static const u16 trans_tbl_jpege[] = {
+	100, 101, 102, 103, 104, 105, 106, 107,
+	108, 109, 110,
+};
+
+static const u16 trans_tbl_jpege_osd[] = {
+	81, 82, 90, 91, 99, 100, 108, 109,
+	117, 118, 126, 127, 135, 136, 144, 145,
+};
+
 static struct mpp_trans_info trans_rkvenc_v2[] = {
 	[RKVENC_FMT_H264E] = {
 		.count = ARRAY_SIZE(trans_tbl_h264e_v2),
@@ -400,6 +506,33 @@ static struct mpp_trans_info trans_rkvenc_v2[] = {
 	},
 };
 
+static struct mpp_trans_info trans_rkvenc_540c[] = {
+	[RKVENC_FMT_H264E] = {
+		.count = ARRAY_SIZE(trans_tbl_h264e_540c),
+		.table = trans_tbl_h264e_540c,
+	},
+	[RKVENC_FMT_H264E_OSD] = {
+		.count = ARRAY_SIZE(trans_tbl_h264e_540c_osd),
+		.table = trans_tbl_h264e_540c_osd,
+	},
+	[RKVENC_FMT_H265E] = {
+		.count = ARRAY_SIZE(trans_tbl_h265e_540c),
+		.table = trans_tbl_h265e_540c,
+	},
+	[RKVENC_FMT_H265E_OSD] = {
+		.count = ARRAY_SIZE(trans_tbl_h265e_540c_osd),
+		.table = trans_tbl_h265e_540c_osd,
+	},
+	[RKVENC_FMT_JPEGE] = {
+		.count = ARRAY_SIZE(trans_tbl_jpege),
+		.table = trans_tbl_jpege,
+	},
+	[RKVENC_FMT_JPEGE_OSD] = {
+		.count = ARRAY_SIZE(trans_tbl_jpege_osd),
+		.table = trans_tbl_jpege_osd,
+	},
+};
+
 static bool req_over_class(struct mpp_request *req,
 			   struct rkvenc_task *task, int class)
 {
@@ -423,6 +556,7 @@ static int rkvenc_free_class_msg(struct rkvenc_task *task)
 
 	for (i = 0; i < reg_class; i++) {
 		kfree(task->reg[i].data);
+		task->reg[i].data = NULL;
 		task->reg[i].size = 0;
 	}
 
@@ -567,8 +701,11 @@ static int rkvenc_extract_task_msg(struct mpp_session *session,
 				wreq = &task->w_reqs[task->w_req_cnt];
 				rkvenc_update_req(task, j, req, wreq);
 				data = rkvenc_get_class_reg(task, wreq->offset);
-				if (!data)
+				if (!data) {
+					mpp_err("get class reg fail, offset %08x\n", wreq->offset);
+					ret = -EINVAL;
 					goto fail;
+				}
 				if (copy_from_user(data, wreq->data, wreq->size)) {
 					mpp_err("copy_from_user fail, offset %08x\n", wreq->offset);
 					ret = -EIO;
@@ -1837,6 +1974,14 @@ static const struct mpp_dev_var rkvenc_v2_data = {
 	.dev_ops = &rkvenc_dev_ops_v2,
 };
 
+static const struct mpp_dev_var rkvenc_540c_data = {
+	.device_type = MPP_DEVICE_RKVENC,
+	.hw_info = &rkvenc_540c_hw_info.hw,
+	.trans_info = trans_rkvenc_540c,
+	.hw_ops = &rkvenc_hw_ops,
+	.dev_ops = &rkvenc_dev_ops_v2,
+};
+
 static const struct mpp_dev_var rkvenc_ccu_data = {
 	.device_type = MPP_DEVICE_RKVENC,
 	.hw_info = &rkvenc_v2_hw_info.hw,
@@ -1850,6 +1995,12 @@ static const struct of_device_id mpp_rkvenc_dt_match[] = {
 		.compatible = "rockchip,rkv-encoder-v2",
 		.data = &rkvenc_v2_data,
 	},
+#ifdef CONFIG_CPU_RK3528
+	{
+		.compatible = "rockchip,rkv-encoder-rk3528",
+		.data = &rkvenc_540c_data,
+	},
+#endif
 #ifdef CONFIG_CPU_RK3588
 	{
 		.compatible = "rockchip,rkv-encoder-v2-core",