From df00b8368c57726d59c96740fe0c2abdc80574b6 Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Mon, 16 Nov 2020 15:53:20 +0800 Subject: [PATCH] clk: rockchip: rk3568: fix up the spi clk Fix up the TRM and RXBB are not sync. Signed-off-by: Elaine Zhang Change-Id: I8d9bec5292686169707a945759c4389919c3430a --- drivers/clk/rockchip/clk-rk3568.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c index 81b4a4d7d4ba..7b140daa9f53 100644 --- a/drivers/clk/rockchip/clk-rk3568.c +++ b/drivers/clk/rockchip/clk-rk3568.c @@ -288,6 +288,7 @@ PNAME(gpll100_gpll75_cpll50_xin24m_p) = { "gpll_100m", "gpll_75m", "cpll_50m", " PNAME(xin24m_gpll100_cpll100_p) = { "xin24m", "gpll_100m", "cpll_100m" }; PNAME(gpll_cpll_usb480m_p) = { "gpll", "cpll", "usb480m" }; PNAME(gpll100_xin24m_cpll100_p) = { "gpll_100m", "xin24m", "cpll_100m" }; +PNAME(gpll200_xin24m_cpll100_p) = { "gpll_200m", "xin24m", "cpll_100m" }; PNAME(xin24m_32k_p) = { "xin24m", "clk_rtc_32k" }; PNAME(cpll500_gpll400_gpll300_xin24m_p) = { "cpll_500m", "gpll_400m", "gpll_300m", "xin24m" }; PNAME(gpll400_gpll300_gpll200_xin24m_p) = { "gpll_400m", "gpll_300m", "gpll_200m", "xin24m" }; @@ -1356,22 +1357,22 @@ static struct rockchip_clk_branch rk3568_clk_branches[] __initdata = { RK3568_CLKGATE_CON(30), 9, GFLAGS), GATE(PCLK_SPI0, "pclk_spi0", "pclk_bus", 0, RK3568_CLKGATE_CON(30), 10, GFLAGS), - COMPOSITE_NODIV(CLK_SPI0, "clk_spi0", gpll100_xin24m_cpll100_p, 0, + COMPOSITE_NODIV(CLK_SPI0, "clk_spi0", gpll200_xin24m_cpll100_p, 0, RK3568_CLKSEL_CON(72), 0, 1, MFLAGS, RK3568_CLKGATE_CON(30), 11, GFLAGS), GATE(PCLK_SPI1, "pclk_spi1", "pclk_bus", 0, RK3568_CLKGATE_CON(30), 12, GFLAGS), - COMPOSITE_NODIV(CLK_SPI1, "clk_spi1", gpll100_xin24m_cpll100_p, 0, + COMPOSITE_NODIV(CLK_SPI1, "clk_spi1", gpll200_xin24m_cpll100_p, 0, RK3568_CLKSEL_CON(72), 2, 1, MFLAGS, RK3568_CLKGATE_CON(30), 13, GFLAGS), GATE(PCLK_SPI2, "pclk_spi2", "pclk_bus", 0, RK3568_CLKGATE_CON(30), 14, GFLAGS), - COMPOSITE_NODIV(CLK_SPI2, "clk_spi2", gpll100_xin24m_cpll100_p, 0, + COMPOSITE_NODIV(CLK_SPI2, "clk_spi2", gpll200_xin24m_cpll100_p, 0, RK3568_CLKSEL_CON(72), 4, 1, MFLAGS, RK3568_CLKGATE_CON(30), 15, GFLAGS), GATE(PCLK_SPI3, "pclk_spi3", "pclk_bus", 0, RK3568_CLKGATE_CON(31), 0, GFLAGS), - COMPOSITE_NODIV(CLK_SPI3, "clk_spi3", gpll100_xin24m_cpll100_p, 0, + COMPOSITE_NODIV(CLK_SPI3, "clk_spi3", gpll200_xin24m_cpll100_p, 0, RK3568_CLKSEL_CON(72), 6, 1, MFLAGS, RK3568_CLKGATE_CON(31), 1, GFLAGS), GATE(PCLK_PWM1, "pclk_pwm1", "pclk_bus", 0, RK3568_CLKGATE_CON(31), 10, GFLAGS), COMPOSITE_NODIV(CLK_PWM1, "clk_pwm1", gpll100_xin24m_cpll100_p, 0,