From df0cb947c3e99d8f7249b92bd0f26235cc1ddaf2 Mon Sep 17 00:00:00 2001
From: Zefa Chen <zefa.chen@rock-chips.com>
Date: Tue, 8 Mar 2022 20:33:03 +0800
Subject: [PATCH] ARM: dts: rockchip: add vicap and csi2 for rv1106

Signed-off-by: Zefa Chen <zefa.chen@rock-chips.com>
Change-Id: I6badb39a4ccdf6f35a390b6782bb927ea08adeb3
---
 arch/arm/boot/dts/rv1106.dtsi | 95 +++++++++++++++++++++++++++++++++++
 1 file changed, 95 insertions(+)

diff --git a/arch/arm/boot/dts/rv1106.dtsi b/arch/arm/boot/dts/rv1106.dtsi
index 682767a0e2cc..04d0c175cf2e 100644
--- a/arch/arm/boot/dts/rv1106.dtsi
+++ b/arch/arm/boot/dts/rv1106.dtsi
@@ -31,6 +31,8 @@
 		i2c2 = &i2c2;
 		i2c3 = &i2c3;
 		i2c4 = &i2c4;
+		rkcif_mipi_lvds0 = &rkcif_mipi_lvds;
+		rkcif_mipi_lvds1 = &rkcif_mipi_lvds1;
 		serial0 = &uart0;
 		serial1 = &uart1;
 		serial2 = &uart2;
@@ -106,6 +108,42 @@
 		};
 	};
 
+	rkcif_dvp: rkcif-dvp {
+		compatible = "rockchip,rkcif-dvp";
+		rockchip,hw = <&rkcif>;
+		status = "disabled";
+	};
+
+	rkcif_dvp_sditf: rkcif-dvp-sditf {
+		compatible = "rockchip,rkcif-sditf";
+		rockchip,cif = <&rkcif_dvp>;
+		status = "disabled";
+	};
+
+	rkcif_mipi_lvds: rkcif-mipi-lvds {
+		compatible = "rockchip,rkcif-mipi-lvds";
+		rockchip,hw = <&rkcif>;
+		status = "disabled";
+	};
+
+	rkcif_mipi_lvds_sditf: rkcif-mipi-lvds-sditf {
+		compatible = "rockchip,rkcif-sditf";
+		rockchip,cif = <&rkcif_mipi_lvds>;
+		status = "disabled";
+	};
+
+	rkcif_mipi_lvds1: rkcif-mipi-lvds1 {
+		compatible = "rockchip,rkcif-mipi-lvds";
+		rockchip,hw = <&rkcif>;
+		status = "disabled";
+	};
+
+	rkcif_mipi_lvds1_sditf: rkcif-mipi-lvds1-sditf {
+		compatible = "rockchip,rkcif-sditf";
+		rockchip,cif = <&rkcif_mipi_lvds1>;
+		status = "disabled";
+	};
+
 	rkisp_vir0: rkisp-vir0 {
 		compatible = "rockchip,rkisp-vir";
 		rockchip,hw = <&rkisp>;
@@ -816,6 +854,63 @@
 		status = "disabled";
 	};
 
+	rkcif: rkcif@ffa10000 {
+		compatible = "rockchip,rv1106-cif";
+		reg = <0xffa10000 0x10000>;
+		reg-names = "cif_regs";
+		interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "cif-intr";
+		clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>,
+			 <&cru DCLK_VICAP>, <&cru PCLK_VICAP>,
+			 <&cru I0CLK_VICAP>, <&cru I1CLK_VICAP>,
+			 <&cru RX0PCLK_VICAP>, <&cru RX1PCLK_VICAP>,
+			 <&cru ISP0CLK_VICAP>;
+		clock-names = "aclk_cif","hclk_cif",
+			      "dclk_cif", "pclk_cif",
+			      "i0clk_cif", "i1clk_cif",
+			      "rx0clk_cif", "rx1clk_cif",
+			      "isp0clk_cif";
+		resets = <&cru SRST_A_VICAP>, <&cru SRST_H_VICAP>,
+			 <&cru SRST_D_VICAP>, <&cru SRST_P_VICAP>,
+			 <&cru SRST_VICAP_I0>, <&cru SRST_VICAP_I1>,
+			 <&cru SRST_VICAP_RX0>, <&cru SRST_VICAP_RX1>,
+			 <&cru SRST_VICAP_ISP0>;
+		reset-names = "rst_cif_a","rst_cif_h",
+			      "rst_cif_d", "rst_cif_p",
+			      "rst_cif_i0", "rst_cif_i1",
+			      "rst_cif_rx0", "rst_cif_rx1",
+			      "rst_cif_isp0";
+		status = "disabled";
+	};
+
+	mipi0_csi2: mipi-csi2@ffa20000 {
+		compatible = "rockchip,rk3588-mipi-csi2";
+		reg = <0xffa20000 0x10000>;
+		reg-names = "csihost_regs";
+		interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "csi-intr1", "csi-intr2";
+		clocks = <&cru PCLK_CSIHOST0>;
+		clock-names = "pclk_csi2host";
+		resets = <&cru SRST_P_CSIHOST0>;
+		reset-names = "srst_csihost_p";
+		status = "disabled";
+	};
+
+	mipi1_csi2: mipi-csi2@ffa30000 {
+		compatible = "rockchip,rk3588-mipi-csi2";
+		reg = <0xffa30000 0x10000>;
+		reg-names = "csihost_regs";
+		interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "csi-intr1", "csi-intr2";
+		clocks = <&cru PCLK_CSIHOST1>;
+		clock-names = "pclk_csi2host";
+		resets = <&cru SRST_P_CSIHOST1>;
+		reset-names = "srst_csihost_p";
+		status = "disabled";
+	};
+
 	rkvenc: rkvenc@ffa50000 {
 		compatible = "rockchip,rkv-encoder-rv1106";
 		reg = <0xffa50000 0x6000>;