dtv_demod: TL1 timeshift display have a lot mosaic [1/1]

PD#SWPL-2618

Problem:
TL1 timeshift display have a lot mosaic

Solution:
tune ts clk to a smaller value

Verify:
verified by t962x2_x301

Change-Id: I89c8cdb3317e42101fc8f161436d33ccd0761945
Signed-off-by: Zhiwei Yuan <zhiwei.yuan@amlogic.com>

drivers/amlogic/media/dtv_demod/amlfrontend.c

@@ -77,7 +77,7 @@ module_param(std_lock_timeout, int, 0644);
 static char *demod_version = "V0.03";
 
 
-int aml_demod_debug = DBG_INFO|DBG_ATSC;
+int aml_demod_debug = DBG_INFO;
 
 
 #if 0
@@ -1119,7 +1119,7 @@ static int Gxtv_Demod_Dvbc_Init(/*struct aml_fe_dev *dev, */int mode)
 
 	if (is_ic_ver(IC_VER_TL1)) {
 		sys.adc_clk = Adc_Clk_24M;
-		sys.demod_clk = Demod_Clk_250M;
+		sys.demod_clk = Demod_Clk_167M;
 		demod_status.tmp = Cry_mode;
 	}
 
@@ -1766,11 +1766,15 @@ static int gxtv_demod_atsc_set_frontend(struct dvb_frontend *fe)
 			param_j83b.symb_rate = 5361;
 
 		if (is_ic_ver(IC_VER_TL1)) {
-			nco_rate = ((demod_status.adc_freq / 1000) * 256)
-				/ 250 + 2;
+			//for timeshift mosaic
+			demod_status.clk_freq = Demod_Clk_167M;
+			nco_rate = (demod_status.adc_freq * 256)
+				/ demod_status.clk_freq + 2;
 			front_write_reg_v4(0x20,
 				((front_read_reg_v4(0x20) & ~0xff)
 				| (nco_rate & 0xff)));
+			front_write_reg_v4(0x2f, 0x5);//for timeshift mosaic
+			dd_tvafe_hiu_reg_write(0x1d0, 0x502);//sys_clk=167M
 		}
 
 		dvbc_set_ch(&demod_status, /*&demod_i2c, */&param_j83b);
@@ -1780,6 +1784,8 @@ static int gxtv_demod_atsc_set_frontend(struct dvb_frontend *fe)
 			set_j83b_filter_reg_v4();
 			qam_write_reg(0x12, 0x50e1000);
 			qam_write_reg(0x30, 0x41f2f69);
+			//for timeshift mosaic issue
+			//qam_write_reg(0x84, 0x2190000);
 		}
 
 	} else if (c->modulation > QAM_AUTO) {
@@ -1801,6 +1807,7 @@ static int gxtv_demod_atsc_set_frontend(struct dvb_frontend *fe)
 					0x16e3600);
 			}
 
+			atsc_write_reg_v4(0x12, 0x18);//for timeshift mosaic
 			Val_0x20.bits = atsc_read_reg_v4(ATSC_CNTR_REG_0X20);
 			Val_0x20.b.cpu_rst = 1;
 			atsc_write_reg_v4(ATSC_CNTR_REG_0X20, Val_0x20.bits);
@@ -2218,7 +2225,10 @@ int Gxtv_Demod_Atsc_Init(void/*struct aml_fe_dev *dev*/)
 	/* 0 -DVBC, 1-DVBT, ISDBT, 2-ATSC*/
 	demod_status.dvb_mode = Gxtv_Atsc;
 	sys.adc_clk = Adc_Clk_24M;    /*Adc_Clk_26M;*/
-	sys.demod_clk = Demod_Clk_225M;  /*Demod_Clk_71M;//Demod_Clk_78M;*/
+	if (is_ic_ver(IC_VER_TL1))
+		sys.demod_clk = Demod_Clk_250M;
+	else
+		sys.demod_clk = Demod_Clk_225M;
 	demod_status.ch_if = 5000;
 	demod_status.tmp = Adc_mode;
 	/*demod_set_sys(&demod_status, &i2c, &sys);*/

drivers/amlogic/media/dtv_demod/demod_func.c

@@ -133,8 +133,12 @@ void adc_dpll_setup(int clk_a, int clk_b, int clk_sys, int dvb_mode)
 	int sts_pll;
 
 	if (is_ic_ver(IC_VER_TL1)) {
-		dtvpll_init_flag(1);
-		return;
+		if (clk_b == Adc_Clk_24M) {
+			dtvpll_init_flag(1);
+			return;
+		} else if (clk_b == Adc_Clk_25M) {
+			//going on to set 25M clk
+		}
 	}
 
 	adc_pll_cntl.d32 = 0;
@@ -996,7 +1000,7 @@ int demod_set_sys(struct aml_demod_sta *demod_sta,
 	dvb_mode = demod_sta->dvb_mode;
 	clk_adc = demod_sys->adc_clk;
 	clk_dem = demod_sys->demod_clk;
-	nco_rate = ((clk_adc / 1000) * 256) / 224 + 2;
+	nco_rate = (clk_adc * 256) / clk_dem + 2;
 	PR_DBG
 	    ("demod_set_sys,clk_adc is %d,clk_demod is %d\n",
 	     clk_adc, clk_dem);
@@ -1076,11 +1080,13 @@ int demod_set_sys(struct aml_demod_sta *demod_sta,
 				| (nco_rate & 0xff)));
 		front_write_reg_v4(0x20, (front_read_reg_v4(0x20) | (1 << 8)));
 	} else if (is_ic_ver(IC_VER_TL1) && (dvb_mode == Gxtv_Dvbc)) {
-		nco_rate = ((clk_adc / 1000) * 256) / 250 + 2;
+		nco_rate = (clk_adc * 256) / clk_dem + 2;
 		demod_write_reg(DEMOD_TOP_REGC, 0x11);
 		front_write_reg_v4(0x20, ((front_read_reg_v4(0x20) & ~0xff)
 				| (nco_rate & 0xff)));
 		front_write_reg_v4(0x20, (front_read_reg_v4(0x20) | (1 << 8)));
+		front_write_reg_v4(0x2f, 0x5);//for timsshift mosaic
+		dd_tvafe_hiu_reg_write(0x1d0, 0x502);//sys_clk=167M
 	}
 
 	demod_sta->adc_freq = clk_adc;

drivers/amlogic/media/dtv_demod/dtmb_func.c

@@ -206,6 +206,9 @@ void dtmb_initial(struct aml_demod_sta *demod_sta)
 			dtmb_write_reg(DTMB_FRONT_SRC_CONFIG1, 0x131a747d);
 			dtmb_write_reg(0x5b << 2, 0x4d6a0a25);
 		}
+
+		//for timeshift issue(chuangcheng test)
+		dtmb_write_reg(0x4e << 2, 0x256cf604);
 	} else {
 		dtmb_register_reset();
 		dtmb_all_reset();

drivers/amlogic/media/dtv_demod/dvbc_v3.c

@@ -196,7 +196,10 @@ void dvbc_reg_initial(struct aml_demod_sta *demod_sta)
 
 	clk_freq = demod_sta->clk_freq;	/* kHz */
 	/*no use adc_freq = demod_sta->adc_freq;*/	/* kHz */
-	adc_freq  = get_adc_freq();/*24000*/;
+	if (is_ic_ver(IC_VER_TL1))
+		adc_freq  = demod_sta->adc_freq;
+	else
+		adc_freq  = get_adc_freq();/*24000*/;
 	adc_format = 1;
 	/*ary no use tuner = demod_sta->tuner;*/
 	ch_mode = demod_sta->ch_mode;

drivers/amlogic/media/dtv_demod/include/amlfrontend.h

@@ -57,6 +57,7 @@ enum Gxtv_Demod_Dvb_Mode {
 
 #define Adc_Clk_25M                     25000	/* dtmb */
 #define Demod_Clk_100M    100000	/*  */
+#define Demod_Clk_167M    167000	/*  */
 #define Demod_Clk_180M    180000	/*  */
 #define Demod_Clk_200M    200000	/*  */
 #define Demod_Clk_225M    225000

drivers/amlogic/media/vin/tvin/tvafe/tvafe_general.c

@@ -888,6 +888,23 @@ int adc_set_pll_cntl(bool on, unsigned int module_sel, void *pDtvPara)
 			W_HIU_REG(HHI_DEMOD_CLK_CNTL, 0x1000502);
 
 			adc_pll_lock_cnt = 1;
+		} else if (tvafe_cpu_type() == CPU_TYPE_TL1) {
+			do {//25M
+				W_HIU_REG(HHI_ADC_PLL_CNTL0_TL1, 0x001104c8);
+				W_HIU_REG(HHI_ADC_PLL_CNTL0_TL1, 0x301104c8);
+				W_HIU_REG(HHI_ADC_PLL_CNTL1_TL1, 0x03000000);
+				W_HIU_REG(HHI_ADC_PLL_CNTL2_TL1, 0xe1800000);
+				W_HIU_REG(HHI_ADC_PLL_CNTL3_TL1, 0x48681c00);
+				W_HIU_REG(HHI_ADC_PLL_CNTL4_TL1, 0x88770290);
+				W_HIU_REG(HHI_ADC_PLL_CNTL5_TL1, 0x39272000);
+				W_HIU_REG(HHI_ADC_PLL_CNTL6_TL1, 0x56540000);
+				W_HIU_REG(HHI_ADC_PLL_CNTL0_TL1, 0x101104c8);
+
+				udelay(100);
+				adc_pll_lock_cnt++;
+			} while (!R_HIU_BIT(HHI_ADC_PLL_CNTL0_TL1, 31, 1) &&
+				(adc_pll_lock_cnt < 10));
+
 		} else {
 			/*is_meson_gxtvbb_cpu()*/
 			W_HIU_REG(HHI_ADC_PLL_CNTL3, 0x8a2a2110);/*reset*/