diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 5aa34b06d3a4..2362146b29e8 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -984,6 +984,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rv1106g-38x38-ipc-v10.dtb \ rv1106g-38x38-ipc-v10-spi-nand.dtb \ rv1106g-evb1-mcu-display-v11.dtb \ + rv1106g-evb1-mcu-display-v20.dtb \ rv1106g-evb1-rgb-display-v11.dtb \ rv1106g-evb1-v10.dtb \ rv1106g-evb1-v11.dtb \ diff --git a/arch/arm/boot/dts/rv1103g-evb-mcu-display-v11.dts b/arch/arm/boot/dts/rv1103g-evb-mcu-display-v11.dts index 5d1c51bb86a1..e62f08d7c060 100644 --- a/arch/arm/boot/dts/rv1103g-evb-mcu-display-v11.dts +++ b/arch/arm/boot/dts/rv1103g-evb-mcu-display-v11.dts @@ -91,22 +91,30 @@ status = "okay"; rockchip,data-sync-bypass; pinctrl-names = "default"; + /* + * rgb3x8_pins for RGB3x8(8bit) + * rgb565_pins for RGB565(16bit) + */ pinctrl-0 = <&rgb3x8_pins>; /* * 320x480 RGB/MCU screen K350C4516T */ mcu_panel: mcu-panel { + /* + * MEDIA_BUS_FMT_RGB888_3X8 for RGB3x8(8bit) + * MEDIA_BUS_FMT_RGB565_1X16 for RGB565(16bit) + */ bus-format = ; backlight = <&backlight>; enable-gpios = <&gpio3 RK_PC7 GPIO_ACTIVE_LOW>; enable-delay-ms = <20>; reset-gpios = <&gpio3 RK_PD0 GPIO_ACTIVE_LOW>; - reset-value = <0>; reset-delay-ms = <10>; prepare-delay-ms = <20>; unprepare-delay-ms = <20>; disable-delay-ms = <20>; + init-delay-ms = <10>; width-mm = <217>; height-mm = <136>; @@ -161,20 +169,31 @@ 00 00 01 36 01 00 01 48 - 00 00 01 3a //interface mode control - 01 00 01 77 //spi rgb:66(r1 r4 r5) mcu parallel: 55(r2 r3 r6) - // mcu serial: 77(r1 r3 r6) + 00 00 01 3a + 01 00 01 66 /* + * interface pixel format: + * 66 for RGB3x8(8bit) + * 55 for RGB565(16bit) + */ - 00 00 01 b0 //interface mode control + 00 00 01 b0 01 00 01 00 - 00 00 01 b1 //frame rate 70hz - 01 00 01 b0 + 00 00 01 b1 + 01 00 01 70 /* + * frame rate control: + * 70 (45hz) for RGB3x8(8bit) + * a0 (60hz) for RGB565(16bit) + */ 01 00 01 11 00 00 01 b4 01 00 01 02 - 00 00 01 B6 //RGB/MCU Interface Control - 01 00 01 02 //02 mcu, 32 rgb + 00 00 01 B6 + 01 00 01 02 /* + * display function control: + * 32 for RGB + * 02 for MCU + */ 01 00 01 02 00 00 01 b7 @@ -208,7 +227,11 @@ native-mode = <&kd050fwfba002_timing>; kd050fwfba002_timing: timing0 { - clock-frequency = <20000000>; + /* + * 7840125 for frame rate 45Hz + * 10453500 for frame rate 60Hz + */ + clock-frequency = <7840125>; hactive = <320>; vactive = <480>; hback-porch = <10>; @@ -267,12 +290,25 @@ &vop { status = "okay"; + /* + * Default config is as follows: + * + * mcu-pix-total = <9>; + * mcu-cs-pst = <1>; + * mcu-cs-pend = <8>; + * mcu-rw-pst = <2>; + * mcu-rw-pend = <5>; + * mcu-hold-mode = <0>; // default set to 0 + * + * To increase the frame rate, reduce all parameters because + * the max dclk rate of mcu is 150M in rv1103/rv1106. + */ mcu-timing { - mcu-pix-total = <9>; + mcu-pix-total = <5>; mcu-cs-pst = <1>; - mcu-cs-pend = <8>; + mcu-cs-pend = <4>; mcu-rw-pst = <2>; - mcu-rw-pend = <5>; + mcu-rw-pend = <3>; mcu-hold-mode = <0>; // default set to 0 }; diff --git a/arch/arm/boot/dts/rv1106-evb-ext-mcu-v10.dtsi b/arch/arm/boot/dts/rv1106-evb-ext-mcu-v10.dtsi index cbc2e6ac6a16..2ab415b35d4f 100644 --- a/arch/arm/boot/dts/rv1106-evb-ext-mcu-v10.dtsi +++ b/arch/arm/boot/dts/rv1106-evb-ext-mcu-v10.dtsi @@ -81,6 +81,10 @@ status = "okay"; rockchip,data-sync-bypass; pinctrl-names = "default"; + /* + * rgb3x8_pins for RGB3x8(8bit) + * rgb565_pins for RGB565(16bit) + */ pinctrl-0 = <&rgb565_pins>; /* @@ -88,19 +92,19 @@ */ mcu_panel: mcu-panel { /* - * MEDIA_BUS_FMT_RGB888_3X8 for serial mcu - * MEDIA_BUS_FMT_RGB565_1X16 for parallel mcu + * MEDIA_BUS_FMT_RGB888_3X8 for RGB3x8(8bit) + * MEDIA_BUS_FMT_RGB565_1X16 for RGB565(16bit) */ bus-format = ; backlight = <&backlight>; enable-gpios = <&gpio1 RK_PA3 GPIO_ACTIVE_LOW>; enable-delay-ms = <20>; reset-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_LOW>; - reset-value = <0>; reset-delay-ms = <10>; prepare-delay-ms = <20>; unprepare-delay-ms = <20>; disable-delay-ms = <20>; + init-delay-ms = <10>; width-mm = <217>; height-mm = <136>; @@ -155,20 +159,31 @@ 00 00 01 36 01 00 01 48 - 00 00 01 3a //interface mode control - 01 00 01 55 //spi rgb:66(r1 r4 r5) mcu parallel: 55(r2 r3 r6) - // mcu serial: 77(r1 r3 r6) + 00 00 01 3a + 01 00 01 55 /* + * interface pixel format: + * 66 for RGB3x8(8bit) + * 55 for RGB565(16bit) + */ - 00 00 01 b0 //interface mode control + 00 00 01 b0 01 00 01 00 - 00 00 01 b1 //frame rate 70hz - 01 00 01 b0 + 00 00 01 b1 + 01 00 01 a0 /* + * frame rate control: + * 70 (45hz) for RGB3x8(8bit) + * a0 (60hz) for RGB565(16bit) + */ 01 00 01 11 00 00 01 b4 01 00 01 02 - 00 00 01 B6 //RGB/MCU Interface Control - 01 00 01 02 //02 mcu, 32 rgb + 00 00 01 B6 + 01 00 01 02 /* + * display function control: + * 32 for RGB + * 02 for MCU + */ 01 00 01 02 00 00 01 b7 @@ -202,7 +217,11 @@ native-mode = <&kd050fwfba002_timing>; kd050fwfba002_timing: timing0 { - clock-frequency = <20000000>; + /* + * 7840125 for frame rate 45Hz + * 10453500 for frame rate 60Hz + */ + clock-frequency = <10453500>; hactive = <320>; vactive = <480>; hback-porch = <10>; @@ -261,12 +280,25 @@ &vop { status = "okay"; + /* + * Default config is as follows: + * + * mcu-pix-total = <9>; + * mcu-cs-pst = <1>; + * mcu-cs-pend = <8>; + * mcu-rw-pst = <2>; + * mcu-rw-pend = <5>; + * mcu-hold-mode = <0>; // default set to 0 + * + * To increase the frame rate, reduce all parameters because + * the max dclk rate of mcu is 150M in rv1103/rv1106. + */ mcu-timing { - mcu-pix-total = <9>; + mcu-pix-total = <5>; mcu-cs-pst = <1>; - mcu-cs-pend = <8>; + mcu-cs-pend = <4>; mcu-rw-pst = <2>; - mcu-rw-pend = <5>; + mcu-rw-pend = <3>; mcu-hold-mode = <0>; // default set to 0 }; diff --git a/arch/arm/boot/dts/rv1106.dtsi b/arch/arm/boot/dts/rv1106.dtsi index 4bb093b80aa3..1cf580756db0 100644 --- a/arch/arm/boot/dts/rv1106.dtsi +++ b/arch/arm/boot/dts/rv1106.dtsi @@ -239,6 +239,18 @@ }; }; + mipi0_csi2: mipi0-csi2 { + compatible = "rockchip,rv1106-mipi-csi2"; + rockchip,hw = <&mipi0_csi2_hw>, <&mipi1_csi2_hw>; + status = "disabled"; + }; + + mipi1_csi2: mipi1-csi2 { + compatible = "rockchip,rv1106-mipi-csi2"; + rockchip,hw = <&mipi0_csi2_hw>, <&mipi1_csi2_hw>; + status = "disabled"; + }; + mpp_srv: mpp-srv { compatible = "rockchip,mpp-service"; rockchip,taskqueue-count = <2>; @@ -1175,8 +1187,8 @@ status = "disabled"; }; - mipi0_csi2: mipi-csi2@ffa20000 { - compatible = "rockchip,rk3588-mipi-csi2"; + mipi0_csi2_hw: mipi-csi2-hw@ffa20000 { + compatible = "rockchip,rv1106-mipi-csi2-hw"; reg = <0xffa20000 0x10000>; reg-names = "csihost_regs"; interrupts = , @@ -1186,11 +1198,11 @@ clock-names = "pclk_csi2host", "clk_rxbyte_hs"; resets = <&cru SRST_P_CSIHOST0>; reset-names = "srst_csihost_p"; - status = "disabled"; + status = "okay"; }; - mipi1_csi2: mipi-csi2@ffa30000 { - compatible = "rockchip,rk3588-mipi-csi2"; + mipi1_csi2_hw: mipi-csi2-hw@ffa30000 { + compatible = "rockchip,rv1106-mipi-csi2-hw"; reg = <0xffa30000 0x10000>; reg-names = "csihost_regs"; interrupts = , @@ -1200,7 +1212,7 @@ clock-names = "pclk_csi2host", "clk_rxbyte_hs"; resets = <&cru SRST_P_CSIHOST1>; reset-names = "srst_csihost_p"; - status = "disabled"; + status = "okay"; }; rkvenc: rkvenc@ffa50000 { diff --git a/arch/arm/boot/dts/rv1106g-evb1-mcu-display-v20.dts b/arch/arm/boot/dts/rv1106g-evb1-mcu-display-v20.dts new file mode 100644 index 000000000000..21dbea71e3a7 --- /dev/null +++ b/arch/arm/boot/dts/rv1106g-evb1-mcu-display-v20.dts @@ -0,0 +1,314 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + */ + +/dts-v1/; + +#include +#include "rv1106g-evb1-v11.dts" + +/ { + model = "Rockchip RV1106G EVB1 V11 Board + RK EVB MCU 8BIT Display V20 Ext Board"; + compatible = "rockchip,rv1106g-evb1-mcu-display-v20", "rockchip,rv1106"; + + backlight: backlight { + status = "okay"; + compatible = "pwm-backlight"; + pwms = <&pwm3 0 25000 0>; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <200>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + inactive; + reusable; + size = <0x1000000>; + linux,cma-default; + }; + + drm_logo: drm-logo@00000000 { + compatible = "rockchip,drm-logo"; + reg = <0x0 0x0>; + }; + }; +}; + +&display_subsystem { + status = "okay"; + logo-memory-region = <&drm_logo>; +}; + +&pwm3 { + status = "okay"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm3m1_pins>; +}; + +&rgb { + status = "okay"; + rockchip,data-sync-bypass; + pinctrl-names = "default"; + /* + * rgb3x8_pins for RGB3x8(8bit) + * rgb565_pins for RGB565(16bit) + */ + pinctrl-0 = <&rgb3x8_pins>; + + /* + * 320x480 RGB/MCU screen K350C4516T + */ + mcu_panel: mcu-panel { + /* + * MEDIA_BUS_FMT_RGB888_3X8 for RGB3x8(8bit) + * MEDIA_BUS_FMT_RGB565_1X16 for RGB565(16bit) + */ + bus-format = ; + backlight = <&backlight>; + enable-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>; + enable-delay-ms = <20>; + reset-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; + reset-delay-ms = <10>; + prepare-delay-ms = <20>; + unprepare-delay-ms = <20>; + disable-delay-ms = <20>; + init-delay-ms = <10>; + width-mm = <217>; + height-mm = <136>; + + // type:0 is cmd, 1 is data + panel-init-sequence = [ + //type delay num val1 val2 val3 + 00 00 01 e0 + 01 00 01 00 + 01 00 01 07 + 01 00 01 0f + 01 00 01 0d + 01 00 01 1b + 01 00 01 0a + 01 00 01 3c + + 01 00 01 78 + 01 00 01 4a + 01 00 01 07 + 01 00 01 0e + 01 00 01 09 + 01 00 01 1b + 01 00 01 1e + 01 00 01 0f + + 00 00 01 e1 + 01 00 01 00 + 01 00 01 22 + 01 00 01 24 + 01 00 01 06 + 01 00 01 12 + 01 00 01 07 + 01 00 01 36 + + 01 00 01 47 + 01 00 01 47 + 01 00 01 06 + 01 00 01 0a + 01 00 01 07 + 01 00 01 30 + 01 00 01 37 + 01 00 01 0f + + 00 00 01 c0 + 01 00 01 10 + 01 00 01 10 + + 00 00 01 c1 + 01 00 01 41 + + 00 00 01 c5 + 01 00 01 00 + 01 00 01 22 + 01 00 01 80 + + 00 00 01 36 + 01 00 01 48 + + 00 00 01 3a + 01 00 01 66 /* + * interface pixel format: + * 66 for RGB3x8(8bit) + * 55 for RGB565(16bit) + */ + + 00 00 01 b0 + 01 00 01 00 + + 00 00 01 b1 + 01 00 01 70 /* + * frame rate control: + * 70 (45hz) for RGB3x8(8bit) + * a0 (60hz) for RGB565(16bit) + */ + 01 00 01 11 + 00 00 01 b4 + 01 00 01 02 + 00 00 01 B6 + 01 00 01 02 /* + * display function control: + * 32 for RGB + * 02 for MCU + */ + 01 00 01 02 + + 00 00 01 b7 + 01 00 01 c6 + + 00 00 01 be + 01 00 01 00 + 01 00 01 04 + + 00 00 01 e9 + 01 00 01 00 + + 00 00 01 f7 + 01 00 01 a9 + 01 00 01 51 + 01 00 01 2c + 01 00 01 82 + + 00 78 01 11 + 00 32 01 29 + 00 00 01 2c + ]; + + panel-exit-sequence = [ + //type delay num val1 val2 val3 + 00 0a 01 28 + 00 78 01 10 + ]; + + display-timings { + native-mode = <&kd050fwfba002_timing>; + + kd050fwfba002_timing: timing0 { + /* + * 7840125 for frame rate 45Hz + * 10453500 for frame rate 60Hz + */ + clock-frequency = <7840125>; + hactive = <320>; + vactive = <480>; + hback-porch = <10>; + hfront-porch = <5>; + vback-porch = <10>; + vfront-porch = <5>; + hsync-len = <10>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; + }; + }; + + port { + panel_in_rgb: endpoint { + remote-endpoint = <&rgb_out_panel>; + }; + }; + }; + + ports { + rgb_out: port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + rgb_out_panel: endpoint@0 { + reg = <0>; + remote-endpoint = <&panel_in_rgb>; + }; + }; + }; +}; + +&rgb_in_vop { + status = "okay"; +}; + +&route_rgb { + status = "disabled"; +}; + +/* + * The pins of sdmmc1 and lcd are multiplexed + */ +&sdio { + status = "disabled"; +}; + +&sdio_pwrseq { + status = "disabled"; +}; + +&vop { + status = "okay"; + + /* + * Default config is as follows: + * + * mcu-pix-total = <9>; + * mcu-cs-pst = <1>; + * mcu-cs-pend = <8>; + * mcu-rw-pst = <2>; + * mcu-rw-pend = <5>; + * mcu-hold-mode = <0>; // default set to 0 + * + * To increase the frame rate, reduce all parameters because + * the max dclk rate of mcu is 150M in rv1103/rv1106. + */ + mcu-timing { + mcu-pix-total = <5>; + mcu-cs-pst = <1>; + mcu-cs-pend = <4>; + mcu-rw-pst = <2>; + mcu-rw-pend = <3>; + + mcu-hold-mode = <0>; // default set to 0 + }; +}; diff --git a/arch/arm/boot/dts/rv1106g-evb2-v10.dts b/arch/arm/boot/dts/rv1106g-evb2-v10.dts index 90274546bad1..47b564600757 100644 --- a/arch/arm/boot/dts/rv1106g-evb2-v10.dts +++ b/arch/arm/boot/dts/rv1106g-evb2-v10.dts @@ -107,7 +107,8 @@ reg = <0x30>; clocks = <&cru MCLK_REF_MIPI0>; clock-names = "xvclk"; - pwdn-gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; + pwdn-gpios = <&gpio3 RK_PD2 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&mipi_refclk_out0>; rockchip,camera-module-index = <0>; diff --git a/arch/arm/boot/dts/rv1126.dtsi b/arch/arm/boot/dts/rv1126.dtsi index 1c64f55d9929..2900694f1d2c 100644 --- a/arch/arm/boot/dts/rv1126.dtsi +++ b/arch/arm/boot/dts/rv1126.dtsi @@ -353,6 +353,12 @@ }; }; + mipi_csi2: mipi-csi2 { + compatible = "rockchip,rv1126-mipi-csi2"; + rockchip,hw = <&mipi_csi2_hw>; + status = "disabled"; + }; + mpp_srv: mpp-srv { compatible = "rockchip,mpp-service"; rockchip,taskqueue-count = <4>; @@ -1861,8 +1867,8 @@ status = "disabled"; }; - mipi_csi2: mipi-csi2@ffb10000 { - compatible = "rockchip,rv1126-mipi-csi2"; + mipi_csi2_hw: mipi-csi2-hw@ffb10000 { + compatible = "rockchip,rv1126-mipi-csi2-hw"; reg = <0xffb10000 0x10000>; reg-names = "csihost_regs"; interrupts = , diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index bf95b466266a..a32d24df97a1 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -72,6 +72,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399pro-rock-pi-n10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-demo1-lp4-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-demo4-ddr4-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-demo4-ddr4-v10-linux.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-demo6-ddr3-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-evb1-ddr4-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-evb1-ddr4-v10-linux.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-evb1-ddr4-v10-spi-nand-linux.dtb @@ -192,6 +193,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-toybrick-x0-linux.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-vehicle-evb-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-vehicle-evb-v20.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-vehicle-evb-v21.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-vehicle-s66-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-evb1-lp4x-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-evb1-lp4x-v10-linux.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-evb2-lp5-v10.dtb diff --git a/arch/arm64/boot/dts/rockchip/px30-dram-default-timing.dtsi b/arch/arm64/boot/dts/rockchip/px30-dram-default-timing.dtsi index c75c5ef4ef2a..99fb02048c82 100644 --- a/arch/arm64/boot/dts/rockchip/px30-dram-default-timing.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30-dram-default-timing.dtsi @@ -70,8 +70,8 @@ phy_lpddr4_dq_drv = ; phy_lpddr4_odt = ; - ddr4_odt_dis_freq = <666>; - phy_ddr4_odt_dis_freq = <666>; + ddr4_odt_dis_freq = <625>; + phy_ddr4_odt_dis_freq = <625>; ddr4_drv = ; ddr4_odt = ; phy_ddr4_ca_drv = ; diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi index 34c8143b8046..ecb7884681b3 100644 --- a/arch/arm64/boot/dts/rockchip/px30.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30.dtsi @@ -2013,11 +2013,11 @@ downdifferential = <20>; system-status-freq = < /*system status freq(KHz)*/ - SYS_STATUS_NORMAL 528000 + SYS_STATUS_NORMAL 666000 SYS_STATUS_REBOOT 450000 SYS_STATUS_SUSPEND 194000 SYS_STATUS_VIDEO_1080P 450000 - SYS_STATUS_BOOST 528000 + SYS_STATUS_BOOST 666000 SYS_STATUS_ISP 666000 SYS_STATUS_PERFORMANCE 1056000 >; @@ -2087,14 +2087,6 @@ opp-microvolt-L2 = <950000>; opp-microvolt-L3 = <950000>; }; - opp-528000000 { - opp-hz = /bits/ 64 <528000000>; - opp-microvolt = <975000>; - opp-microvolt-L0 = <975000>; - opp-microvolt-L1 = <975000>; - opp-microvolt-L2 = <950000>; - opp-microvolt-L3 = <950000>; - }; opp-666000000 { opp-hz = /bits/ 64 <666000000>; opp-microvolt = <1050000>; @@ -2125,11 +2117,6 @@ opp-hz = /bits/ 64 <328000000>; opp-microvolt = <950000>; }; - opp-528000000 { - opp-hz = /bits/ 64 <528000000>; - opp-microvolt = <950000>; - status = "disabled"; - }; opp-666000000 { opp-hz = /bits/ 64 <666000000>; opp-microvolt = <950000>; diff --git a/arch/arm64/boot/dts/rockchip/rk1808.dtsi b/arch/arm64/boot/dts/rockchip/rk1808.dtsi index 297b41269efb..3401beb0837b 100644 --- a/arch/arm64/boot/dts/rockchip/rk1808.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk1808.dtsi @@ -247,6 +247,12 @@ #clock-cells = <0>; }; + mipi_csi2: mipi-csi2 { + compatible = "rockchip,rk1808-mipi-csi2"; + rockchip,hw = <&mipi_csi2_hw>; + status = "disabled"; + }; + psci { compatible = "arm,psci-1.0"; method = "smc"; @@ -1525,8 +1531,8 @@ status = "disabled"; }; - mipi_csi2: mipi-csi2@ffb10000 { - compatible = "rockchip,rk1808-mipi-csi2"; + mipi_csi2_hw: mipi-csi2-hw@ffb10000 { + compatible = "rockchip,rk1808-mipi-csi2-hw"; reg = <0x0 0xffb10000 0x0 0x100>; reg-names = "csihost_regs"; interrupts = , diff --git a/arch/arm64/boot/dts/rockchip/rk3308-evb-ext-v10.dtsi b/arch/arm64/boot/dts/rockchip/rk3308-evb-ext-v10.dtsi index 1c0e66384c16..73089bf04e09 100644 --- a/arch/arm64/boot/dts/rockchip/rk3308-evb-ext-v10.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3308-evb-ext-v10.dtsi @@ -118,19 +118,23 @@ 00 00 01 36 01 00 01 48 - 00 00 01 3a /* interface mode control */ - 01 00 01 66 + 00 00 01 3a //interface pixel format + 01 00 01 66 // bpp cfg + // 3 11 + // 16 55 + // 18 66 + // 24 77 00 00 01 b0 /* interface mode control */ 01 00 01 00 - 00 00 01 b1 /* frame rate 70hz */ - 01 00 01 b0 + 00 00 01 b1 /* frame rate 60hz */ + 01 00 01 a0 01 00 01 11 00 00 01 b4 01 00 01 02 - 00 00 01 B6 /* RGB/MCU Interface Control */ - 01 00 01 32 /* 02 mcu, 32 rgb */ + 00 00 01 B6 + 01 00 01 32 01 00 01 02 00 00 01 b7 @@ -163,7 +167,7 @@ native-mode = <&kd050fwfba002_timing>; kd050fwfba002_timing: timing0 { - clock-frequency = <12000000>; + clock-frequency = <94081500>; hactive = <320>; vactive = <480>; hback-porch = <10>; @@ -232,4 +236,14 @@ &vop { status = "okay"; + + mcu-timing { + mcu-pix-total = <9>; + mcu-cs-pst = <1>; + mcu-cs-pend = <8>; + mcu-rw-pst = <2>; + mcu-rw-pend = <5>; + + mcu-hold-mode = <0>; // default set to 0 + }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3308b-amp.dtsi b/arch/arm64/boot/dts/rockchip/rk3308b-amp.dtsi index 72f3029c62c0..9b7ec9810f99 100644 --- a/arch/arm64/boot/dts/rockchip/rk3308b-amp.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3308b-amp.dtsi @@ -3,6 +3,8 @@ * Copyright (c) 2023 Rockchip Electronics Co., Ltd. */ +#include + / { rockchip_amp: rockchip-amp { compatible = "rockchip,amp"; @@ -12,6 +14,8 @@ pinctrl-names = "default"; pinctrl-0 = <&uart1_xfer>; status = "okay"; + amp-cpu-aff-maskbits = <0x0 0x1 0x1 0x2 0x2 0x4 0x3 0x8>; + amp-irqs = ; }; reserved-memory { diff --git a/arch/arm64/boot/dts/rockchip/rk3308bs-evb-ext-mcu-v10.dtsi b/arch/arm64/boot/dts/rockchip/rk3308bs-evb-ext-mcu-v10.dtsi index 990d00a570a2..095d2e197951 100644 --- a/arch/arm64/boot/dts/rockchip/rk3308bs-evb-ext-mcu-v10.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3308bs-evb-ext-mcu-v10.dtsi @@ -113,19 +113,23 @@ 00 00 01 36 01 00 01 48 - 00 00 01 3a //interface mode control - 01 00 01 55 //spi rgb:66(r1 r4 r5), mcu: 55(r2, r3 r6) + 00 00 01 3a //interface pixel format + 01 00 01 55 // bpp cfg + // 3 11 + // 16 55 + // 18 66 + // 24 77 00 00 01 b0 //interface mode control 01 00 01 00 - 00 00 01 b1 //frame rate 70hz - 01 00 01 b0 + 00 00 01 b1 //frame rate 60hz + 01 00 01 a0 01 00 01 11 00 00 01 b4 01 00 01 02 - 00 00 01 B6 //RGB/MCU Interface Control - 01 00 01 02 //02 mcu, 32 rgb + 00 00 01 B6 + 01 00 01 02 01 00 01 02 00 00 01 b7 @@ -159,7 +163,7 @@ native-mode = <&kd050fwfba002_timing>; kd050fwfba002_timing: timing0 { - clock-frequency = <20000000>; + clock-frequency = <94081500>; hactive = <320>; vactive = <480>; hback-porch = <10>; diff --git a/arch/arm64/boot/dts/rockchip/rk3308bs-evb-mipi-display-v11.dts b/arch/arm64/boot/dts/rockchip/rk3308bs-evb-mipi-display-v11.dts index 751012b37649..de5e68d65145 100644 --- a/arch/arm64/boot/dts/rockchip/rk3308bs-evb-mipi-display-v11.dts +++ b/arch/arm64/boot/dts/rockchip/rk3308bs-evb-mipi-display-v11.dts @@ -18,6 +18,22 @@ status = "disabled"; }; +&lcdc_rgb888_m1 { + rockchip,pins = + /* d18 */ + <3 RK_PA6 3 &pcfg_pull_none_2ma>, + /* d19 */ + <3 RK_PA7 3 &pcfg_pull_none_2ma>, + /* d20 */ + <3 RK_PB0 3 &pcfg_pull_none_2ma>, + /* d21 */ + <3 RK_PB1 3 &pcfg_pull_none_2ma>, + /* d22 */ + <3 RK_PB2 4 &pcfg_pull_none_2ma>, + /* d23 */ + <3 RK_PB3 4 &pcfg_pull_none_2ma>; +}; + &pdm_8ch { pinctrl-names = "default"; pinctrl-0 = <&pdm_m2_clk diff --git a/arch/arm64/boot/dts/rockchip/rk3399-excavator-sapphire.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-excavator-sapphire.dtsi index e17867f04d7b..c12a87057876 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-excavator-sapphire.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-excavator-sapphire.dtsi @@ -10,23 +10,34 @@ compatible = "rockchip,rk3399-sapphire-excavator", "rockchip,rk3399"; rt5651_sound: rt5651-sound { - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,name = "realtek,rt5651-codec"; - simple-audio-card,mclk-fs = <256>; - simple-audio-card,widgets = - "Microphone", "Mic Jack", - "Headphone", "Headphone Jack"; - simple-audio-card,routing = - "Mic Jack", "MICBIAS1", - "IN1P", "Mic Jack", - "Headphone Jack", "HPOL", - "Headphone Jack", "HPOR"; - simple-audio-card,cpu { - sound-dai = <&i2s0>; - }; - simple-audio-card,codec { - sound-dai = <&rt5651>; + status = "okay"; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "realtek,rt5651-codec"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + spk-con-gpio = <&gpio0 11 GPIO_ACTIVE_HIGH>; + hp-det-gpio = <&gpio4 28 GPIO_ACTIVE_HIGH>; + rockchip,format = "i2s"; + rockchip,mclk-fs = <256>; + rockchip,cpu = <&i2s0>; + rockchip,codec = <&rt5651>; + rockchip,audio-routing = + "Headphone", "HPOL", + "Headphone", "HPOR", + "Speaker", "HPOL", + "Speaker", "HPOR", + "Headphone", "Headphone Power", + "Headphone", "Headphone Power", + "Speaker", "Speaker Power", + "Speaker", "Speaker Power", + "IN1P", "Main Mic", + "IN2P", "Headset Mic", + "IN2N", "Headset Mic"; + "Headset Mic", "micbias1"; + play-pause-key { + label = "playpause"; + linux,code = ; + press-threshold-microvolt = <2000>; }; }; @@ -152,8 +163,6 @@ clock-names = "mclk"; pinctrl-names = "default"; pinctrl-0 = <&i2s_8ch_mclk>; - spk-con-gpio = <&gpio0 11 GPIO_ACTIVE_HIGH>; - hp-det-gpio = <&gpio4 28 GPIO_ACTIVE_LOW>; }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator-lp4-linux.dts b/arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator-lp4-linux.dts index da471a636103..54066eeb9826 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator-lp4-linux.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator-lp4-linux.dts @@ -11,6 +11,46 @@ model = "Rockchip RK3399 Excavator Board (Linux Opensource)"; compatible = "rockchip,rk3399-excavator-linux", "rockchip,rk3399"; + backlight: backlight { + compatible = "pwm-backlight"; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <200>; + pwms = <&pwm0 0 25000 0>; + enable-gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>; + }; + vcc_lcd: vcc-lcd { compatible = "regulator-fixed"; regulator-name = "vcc_lcd"; @@ -20,7 +60,7 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-boot-on; - vin-supply = <&vcc5v0_sys>; + vin-supply = <&vcc_sys>; }; panel: panel { @@ -329,17 +369,6 @@ vref-supply = <&vccadc_ref>; }; -&backlight { - status = "okay"; - enable-gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>; -}; - -&cdn_dp { - status = "okay"; - extcon = <&fusb0>; - phys = <&tcphy0_dp>; -}; - &display_subsystem { status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3528-demo6-ddr3-v10.dts b/arch/arm64/boot/dts/rockchip/rk3528-demo6-ddr3-v10.dts new file mode 100644 index 000000000000..26f79a687ae2 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3528-demo6-ddr3-v10.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +#include "rk3528-demo6-ddr3-v10.dtsi" +#include "rk3528-android.dtsi" + +&pdm { + status = "okay"; + pinctrl-0 = <&pdm_clk1 + &pdm_sdi1>; +}; + +&pdmics { + status = "okay"; +}; + +&pdm_mic_array { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3528-demo6-ddr3-v10.dtsi b/arch/arm64/boot/dts/rockchip/rk3528-demo6-ddr3-v10.dtsi new file mode 100644 index 000000000000..228081882c8c --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3528-demo6-ddr3-v10.dtsi @@ -0,0 +1,337 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3528.dtsi" +#include "rk3528-demo.dtsi" + +/ { + model = "Rockchip RK3528 DEMO6 DDR3 V10 Board"; + compatible = "rockchip,rk3528-demo6-ddr3-v10", "rockchip,rk3528"; + + /delete-node/ vcc-ddr-s3; + /delete-node/ vcc-3v3-s3; + /delete-node/ vdd-cpu; + /delete-node/ vdd-logic; + /delete-node/ vdd-0v9-s3; + /delete-node/ vdd-1v8-s3; + + /omit-if-no-ref/ + vcc_sd: vcc-sd { + compatible = "regulator-fixed"; + regulator-boot-on; + gpio = <&gpio4 RK_PA1 GPIO_ACTIVE_LOW>; + regulator-name = "vcc_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3_s3>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h &clkm1_32k_out>; + reset-gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_LOW>; + }; + + /omit-if-no-ref/ + vccio_sd: vccio-sd { + compatible = "regulator-gpio"; + regulator-name = "vccio_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_sys>; + states = <1800000 0x0 + 3300000 0x1>; + }; + + wireless_bluetooth: wireless-bluetooth { + compatible = "bluetooth-platdata"; + //wifi-bt-power-toggle; + uart_rts_gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart2m1_rtsn &bt_enable_h>; + pinctrl-1 = <&uart2m1_gpios>; + BT,reset_gpio = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless_wlan: wireless-wlan { + compatible = "wlan-platdata"; + rockchip,grf = <&grf>; + wifi_chip_type = "aic8800"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq >; + WIFI,host_wake_irq = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>; + //WIFI,reset_gpio = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +&gmac0 { + status = "disabled"; +}; + +&gmac1 { + /* Use rgmii-rxid mode to disable rx delay inside Soc */ + phy-mode = "rgmii-rxid"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + tx_delay = <0x30>; + /* rx_delay = <0x3f>; */ + + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_miim + &rgmii_tx_bus2 + &rgmii_rx_bus2 + &rgmii_rgmii_clk + &rgmii_rgmii_bus + ð_pins>; + + phy-handle = <&rgmii_phy>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + rk805: rk805@18 { + compatible = "rockchip,rk805"; + status = "okay"; + reg = <0x18>; + interrupt-parent = <&gpio4>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + wakeup-source; + gpio-controller; + #gpio-cells = <2>; + #clock-cells = <1>; + clock-output-names = "rk805-clkout1", "rk805-clkout2"; + rk805,system-power-controoler; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc_3v3_s3>; + vcc6-supply = <&vcc5v0_sys>; + + rtc { + status = "okay"; + }; + + pwrkey { + status = "disabled"; + }; + + gpio { + status = "okay"; + }; + + regulators { + vdd_cpu: DCDC_REG1 { + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1450000>; + regulator-init-microvolt = <953000>; + regulator-initial-mode = <0x1>; + regulator-ramp-delay = <12500>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_logic: DCDC_REG2 { + regulator-name = "vdd_logic"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1450000>; + regulator-init-microvolt = <900000>; + regulator-initial-mode = <0x1>; + regulator-ramp-delay = <12500>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-mode = <0x2>; + regulator-on-in-suspend; + regulator-suspend-microvolt = <712500>; + }; + }; + + vcc_ddr_s3: DCDC_REG3 { + regulator-name = "vcc_ddr_s3"; + regulator-initial-mode = <0x1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-mode = <0x2>; + regulator-on-in-suspend; + }; + }; + + vcc_3v3_s3: DCDC_REG4 { + regulator-name = "vcc_3v3_s3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = <0x1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-mode = <0x2>; + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vdd_1v8_s3: LDO_REG1 { + regulator-name = "vdd_1v8_s3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_18emmc: LDO_REG2 { + regulator-name = "vcc_18emmc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v9_s3: LDO_REG3 { + regulator-name = "vdd_0v9_s3"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + }; + }; +}; + +&mdio1 { + rgmii_phy: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + clocks = <&cru CLK_GMAC1_VPU_25M>; + }; +}; + +&pinctrl { + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = + <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-bluetooth { + uart2m1_gpios: uart2m1-gpios { + rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + bt_enable_h: bt-enable-h { + rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; +}; + +&pwm1 { + status = "disabled"; +}; + +&pwm2 { + status = "disabled"; +}; + +&rockchip_suspend { + status = "okay"; + rockchip,sleep-mode-config = < + (0 + |RKPM_SLP_ARMOFF + ) + >; +}; + +&sdio0 { + max-frequency = <200000000>; + no-sd; + no-mmc; + supports-sdio; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + non-removable; + mmc-pwrseq = <&sdio_pwrseq>; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; + post-power-on-delay-ms = <50>; + /delete-property/ rockchip,use-v2-tuning; + sd-uhs-sdr104; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + max-frequency = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; + rockchip,default-sample-phase = <90>; + supports-sd; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + vqmmc-supply = <&vccio_sd>; + vmmc-supply = <&vcc_sd>; + status = "okay"; +}; + +&uart2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart2m1_xfer &uart2m1_ctsn>; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3528.dtsi b/arch/arm64/boot/dts/rockchip/rk3528.dtsi index c3edb864822e..ba30a26d5ead 100644 --- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi @@ -1916,6 +1916,8 @@ rockchip,hw-tshut-temp = <120000>; rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ + nvmem-cells = <&cpu_tsadc_trim_l>, <&cpu_tsadc_trim_h>; + nvmem-cell-names = "trim_l", "trim_h"; status = "disabled"; }; @@ -2316,6 +2318,12 @@ dmc_opp_info: dmc-opp-info@3e { reg = <0x3e 0x6>; }; + cpu_tsadc_trim_l: cpu-tsadc-trim-l@44 { + reg = <0x44 0x1>; + }; + cpu_tsadc_trim_h: cpu-tsadc-trim-h@45 { + reg = <0x45 0x1>; + }; }; dmac: dma-controller@ffd60000 { diff --git a/arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10-mcu-k350c4516t.dts b/arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10-mcu-k350c4516t.dts index d34221e26613..a462ed70f3b3 100644 --- a/arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10-mcu-k350c4516t.dts +++ b/arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10-mcu-k350c4516t.dts @@ -124,20 +124,23 @@ 00 00 01 36 01 00 01 48 - 00 00 01 3a //interface mode control - 01 00 01 55 //spi rgb:66(r1 r4 r5) mcu parallel: 55(r2 r3 r6) - // mcu serial: 77(r1 r3 r6) + 00 00 01 3a //interface pixel format + 01 00 01 55 // bpp cfg + // 3 11 + // 16 55 + // 18 66 + // 24 77 00 00 01 b0 //interface mode control 01 00 01 00 - 00 00 01 b1 //frame rate 70hz - 01 00 01 b0 + 00 00 01 b1 //frame rate 60hz + 01 00 01 a0 01 00 01 11 00 00 01 b4 01 00 01 02 - 00 00 01 B6 //RGB/MCU Interface Control - 01 00 01 02 //02 mcu, 32 rgb + 00 00 01 B6 + 01 00 01 02 01 00 01 02 00 00 01 b7 @@ -171,7 +174,7 @@ native-mode = <&kd050fwfba002_timing>; kd050fwfba002_timing: timing0 { - clock-frequency = <80000000>; + clock-frequency = <94081500>; hactive = <320>; vactive = <480>; hback-porch = <10>; diff --git a/arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10-rgb-k350c4516t.dts b/arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10-rgb-k350c4516t.dts index faaf453266f4..57c317a3bf2d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10-rgb-k350c4516t.dts +++ b/arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10-rgb-k350c4516t.dts @@ -99,19 +99,23 @@ 00 00 01 36 01 00 01 48 - 00 00 01 3a /* interface mode control */ - 01 00 01 66 + 00 00 01 3a //interface pixel format + 01 00 01 66 // bpp cfg + // 3 11 + // 16 55 + // 18 66 + // 24 77 00 00 01 b0 /* interface mode control */ 01 00 01 00 - 00 00 01 b1 /* frame rate 70hz */ - 01 00 01 b0 + 00 00 01 b1 /* frame rate 60hz */ + 01 00 01 a0 01 00 01 11 00 00 01 b4 01 00 01 02 - 00 00 01 B6 /* RGB/MCU Interface Control */ - 01 00 01 32 /* 02 mcu, 32 rgb */ + 00 00 01 B6 + 01 00 01 32 01 00 01 02 00 00 01 b7 @@ -144,7 +148,7 @@ native-mode = <&kd050fwfba002_timing>; kd050fwfba002_timing: timing0 { - clock-frequency = <12000000>; + clock-frequency = <10453500>; hactive = <320>; vactive = <480>; hback-porch = <10>; diff --git a/arch/arm64/boot/dts/rockchip/rk3562.dtsi b/arch/arm64/boot/dts/rockchip/rk3562.dtsi index 7dfaac3306d6..c929325433dd 100644 --- a/arch/arm64/boot/dts/rockchip/rk3562.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3562.dtsi @@ -384,42 +384,42 @@ /* dphy0 full mode */ csi2_dphy0: csi2-dphy0 { compatible = "rockchip,rk3562-csi2-dphy"; - rockchip,hw = <&csi2_dphy0_hw>; + rockchip,hw = <&csi2_dphy0_hw>, <&csi2_dphy1_hw>; status = "disabled"; }; /* dphy0 split mode 01 */ csi2_dphy1: csi2-dphy1 { compatible = "rockchip,rk3562-csi2-dphy"; - rockchip,hw = <&csi2_dphy0_hw>; + rockchip,hw = <&csi2_dphy0_hw>, <&csi2_dphy1_hw>; status = "disabled"; }; /* dphy0 split mode 23 */ csi2_dphy2: csi2-dphy2 { compatible = "rockchip,rk3562-csi2-dphy"; - rockchip,hw = <&csi2_dphy0_hw>; + rockchip,hw = <&csi2_dphy0_hw>, <&csi2_dphy1_hw>; status = "disabled"; }; /* dphy1 full mode */ csi2_dphy3: csi2-dphy3 { compatible = "rockchip,rk3562-csi2-dphy"; - rockchip,hw = <&csi2_dphy1_hw>; + rockchip,hw = <&csi2_dphy0_hw>, <&csi2_dphy1_hw>; status = "disabled"; }; /* dphy1 split mode 01 */ csi2_dphy4: csi2-dphy4 { compatible = "rockchip,rk3562-csi2-dphy"; - rockchip,hw = <&csi2_dphy1_hw>; + rockchip,hw = <&csi2_dphy0_hw>, <&csi2_dphy1_hw>; status = "disabled"; }; /* dphy1 split mode 23 */ csi2_dphy5: csi2-dphy5 { compatible = "rockchip,rk3562-csi2-dphy"; - rockchip,hw = <&csi2_dphy1_hw>; + rockchip,hw = <&csi2_dphy0_hw>, <&csi2_dphy1_hw>; status = "disabled"; }; @@ -536,6 +536,34 @@ status = "disabled"; }; + mipi0_csi2: mipi0-csi2 { + compatible = "rockchip,rk3562-mipi-csi2"; + rockchip,hw = <&mipi0_csi2_hw>, <&mipi1_csi2_hw>, + <&mipi2_csi2_hw>, <&mipi3_csi2_hw>; + status = "disabled"; + }; + + mipi1_csi2: mipi1-csi2 { + compatible = "rockchip,rk3562-mipi-csi2"; + rockchip,hw = <&mipi0_csi2_hw>, <&mipi1_csi2_hw>, + <&mipi2_csi2_hw>, <&mipi3_csi2_hw>; + status = "disabled"; + }; + + mipi2_csi2: mipi2-csi2 { + compatible = "rockchip,rk3562-mipi-csi2"; + rockchip,hw = <&mipi0_csi2_hw>, <&mipi1_csi2_hw>, + <&mipi2_csi2_hw>, <&mipi3_csi2_hw>; + status = "disabled"; + }; + + mipi3_csi2: mipi3-csi2 { + compatible = "rockchip,rk3562-mipi-csi2"; + rockchip,hw = <&mipi0_csi2_hw>, <&mipi1_csi2_hw>, + <&mipi2_csi2_hw>, <&mipi3_csi2_hw>; + status = "disabled"; + }; + psci { compatible = "arm,psci-1.0"; method = "smc"; @@ -1111,9 +1139,9 @@ #reset-cells = <1>; assigned-clocks = - <&cru PLL_GPLL>, <&cru PLL_CPLL>; + <&cru PLL_GPLL>, <&cru PLL_CPLL>, <&cru PLL_HPLL>; assigned-clock-rates = - <1188000000>, <1000000000>; + <1188000000>, <1000000000>, <983040000>; }; i2c0: i2c@ff200000 { @@ -1555,8 +1583,8 @@ status = "disabled"; }; - mipi0_csi2: mipi0-csi2@ff380000 { - compatible = "rockchip,rk3562-mipi-csi2"; + mipi0_csi2_hw: mipi0-csi2-hw@ff380000 { + compatible = "rockchip,rk3562-mipi-csi2-hw"; reg = <0x0 0xff380000 0x0 0x10000>; reg-names = "csihost_regs"; interrupts = , @@ -1566,11 +1594,11 @@ clock-names = "pclk_csi2host"; resets = <&cru SRST_P_CSIHOST0>; reset-names = "srst_csihost_p"; - status = "disabled"; + status = "okay"; }; - mipi1_csi2: mipi1-csi2@ff390000 { - compatible = "rockchip,rk3562-mipi-csi2"; + mipi1_csi2_hw: mipi1-csi2-hw@ff390000 { + compatible = "rockchip,rk3562-mipi-csi2-hw"; reg = <0x0 0xff390000 0x0 0x10000>; reg-names = "csihost_regs"; interrupts = , @@ -1580,11 +1608,11 @@ clock-names = "pclk_csi2host"; resets = <&cru SRST_P_CSIHOST1>; reset-names = "srst_csihost_p"; - status = "disabled"; + status = "okay"; }; - mipi2_csi2: mipi2-csi2@ff3a0000 { - compatible = "rockchip,rk3562-mipi-csi2"; + mipi2_csi2_hw: mipi2-csi2-hw@ff3a0000 { + compatible = "rockchip,rk3562-mipi-csi2-hw"; reg = <0x0 0xff3a0000 0x0 0x10000>; reg-names = "csihost_regs"; interrupts = , @@ -1594,11 +1622,11 @@ clock-names = "pclk_csi2host"; resets = <&cru SRST_P_CSIHOST2>; reset-names = "srst_csihost_p"; - status = "disabled"; + status = "okay"; }; - mipi3_csi2: mipi3-csi2@ff3b0000 { - compatible = "rockchip,rk3562-mipi-csi2"; + mipi3_csi2_hw: mipi3-csi2-hw@ff3b0000 { + compatible = "rockchip,rk3562-mipi-csi2-hw"; reg = <0x0 0xff3b0000 0x0 0x10000>; reg-names = "csihost_regs"; interrupts = , @@ -1608,7 +1636,7 @@ clock-names = "pclk_csi2host"; resets = <&cru SRST_P_CSIHOST3>; reset-names = "srst_csihost_p"; - status = "disabled"; + status = "okay"; }; csi2_dphy0_hw: csi2-dphy0-hw@ff3c0000 { @@ -1619,7 +1647,7 @@ resets = <&cru SRST_P_CSIPHY0>; reset-names = "srst_p_csiphy0"; rockchip,grf = <&sys_grf>; - status = "disabled"; + status = "okay"; }; csi2_dphy1_hw: csi2-dphy1-hw@ff3d0000 { @@ -1630,7 +1658,7 @@ resets = <&cru SRST_P_CSIPHY1>; reset-names = "srst_p_csiphy1"; rockchip,grf = <&sys_grf>; - status = "disabled"; + status = "okay"; }; rkcif: rkcif@ff3e0000 { @@ -2222,6 +2250,8 @@ interrupts = ; clocks = <&cru MCLK_SAI0>, <&cru HCLK_SAI0>; clock-names = "mclk", "hclk"; + assigned-clocks = <&cru CLK_SAI0_SRC>; + assigned-clock-parents = <&cru PLL_HPLL>; dmas = <&dmac 19>, <&dmac 18>; dma-names = "tx", "rx"; resets = <&cru SRST_M_SAI0_8CH>, <&cru SRST_H_SAI0_8CH>; @@ -2244,6 +2274,8 @@ interrupts = ; clocks = <&cru MCLK_SAI1>, <&cru HCLK_SAI1>; clock-names = "mclk", "hclk"; + assigned-clocks = <&cru CLK_SAI1_SRC>; + assigned-clock-parents = <&cru PLL_HPLL>; dmas = <&dmac 21>, <&dmac 20>; dma-names = "tx", "rx"; resets = <&cru SRST_M_SAI1_8CH>, <&cru SRST_H_SAI1_8CH>; @@ -2269,6 +2301,8 @@ interrupts = ; clocks = <&cru MCLK_SAI2>, <&cru HCLK_SAI2>; clock-names = "mclk", "hclk"; + assigned-clocks = <&cru CLK_SAI2_SRC>; + assigned-clock-parents = <&cru PLL_HPLL>; dmas = <&dmac 23>, <&dmac 22>; dma-names = "tx", "rx"; resets = <&cru SRST_M_SAI2_2CH>, <&cru SRST_H_SAI2_2CH>; @@ -2287,6 +2321,8 @@ reg = <0x0 0xff830000 0x0 0x1000>; clocks = <&cru MCLK_PDM>, <&cru HCLK_PDM>; clock-names = "pdm_clk", "pdm_hclk"; + assigned-clocks = <&cru MCLK_PDM>; + assigned-clock-parents = <&cru PLL_HPLL>; dmas = <&dmac 31>; dma-names = "rx"; pinctrl-names = "default"; @@ -2308,6 +2344,8 @@ dma-names = "tx"; clock-names = "mclk", "hclk"; clocks = <&cru MCLK_SPDIF>, <&cru HCLK_SPDIF>; + assigned-clocks = <&cru CLK_SPDIF_SRC>; + assigned-clock-parents = <&cru PLL_HPLL>; #sound-dai-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&spdifm0_pins>; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-toybrick-sd0.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-toybrick-sd0.dtsi index 13692175b129..6041d1a1994c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-toybrick-sd0.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3568-toybrick-sd0.dtsi @@ -207,7 +207,7 @@ &gmac1m1_rgmii_bus ð1m1_pins>; - tx_delay = <0x47>; + tx_delay = <0x30>; rx_delay = <0x28>; phy-handle = <&rgmii_phy1>; diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi index e209d2dcc362..99dea88dd54e 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi @@ -125,8 +125,11 @@ opp-shared; mbist-vmin = <825000 900000 950000>; - nvmem-cells = <&cpu_leakage>, <&core_pvtm>, <&mbist_vmin>, <&cpu_opp_info>; - nvmem-cell-names = "leakage", "pvtm", "mbist-vmin", "opp-info"; + nvmem-cells = <&cpu_leakage>, <&core_pvtm>, <&mbist_vmin>, <&cpu_opp_info>, + <&specification_serial_number>; + nvmem-cell-names = "leakage", "pvtm", "mbist-vmin", "opp-info", + "specification_serial_number"; + rockchip,supported-hw; rockchip,max-volt = <1150000>; rockchip,pvtm-voltage-sel = < 0 84000 0 @@ -150,23 +153,28 @@ 0 1992 75000 >; + /* RK3568 && RK3568M cpu OPPs */ opp-408000000 { + opp-supported-hw = <0xfb 0xffff>; opp-hz = /bits/ 64 <408000000>; opp-microvolt = <850000 850000 1150000>; clock-latency-ns = <40000>; }; opp-600000000 { + opp-supported-hw = <0xfb 0xffff>; opp-hz = /bits/ 64 <600000000>; opp-microvolt = <850000 850000 1150000>; clock-latency-ns = <40000>; }; opp-816000000 { + opp-supported-hw = <0xfb 0xffff>; opp-hz = /bits/ 64 <816000000>; opp-microvolt = <850000 850000 1150000>; clock-latency-ns = <40000>; opp-suspend; }; opp-1104000000 { + opp-supported-hw = <0xfb 0xffff>; opp-hz = /bits/ 64 <1104000000>; opp-microvolt = <900000 900000 1150000>; opp-microvolt-L0 = <900000 900000 1150000>; @@ -176,6 +184,7 @@ clock-latency-ns = <40000>; }; opp-1416000000 { + opp-supported-hw = <0xfb 0xffff>; opp-hz = /bits/ 64 <1416000000>; opp-microvolt = <1025000 1025000 1150000>; opp-microvolt-L0 = <1025000 1025000 1150000>; @@ -185,6 +194,7 @@ clock-latency-ns = <40000>; }; opp-1608000000 { + opp-supported-hw = <0xf9 0xffff>; opp-hz = /bits/ 64 <1608000000>; opp-microvolt = <1100000 1100000 1150000>; opp-microvolt-L0 = <1100000 1100000 1150000>; @@ -194,6 +204,7 @@ clock-latency-ns = <40000>; }; opp-1800000000 { + opp-supported-hw = <0xf9 0xffff>; opp-hz = /bits/ 64 <1800000000>; opp-microvolt = <1150000 1150000 1150000>; opp-microvolt-L0 = <1150000 1150000 1150000>; @@ -203,6 +214,7 @@ clock-latency-ns = <40000>; }; opp-1992000000 { + opp-supported-hw = <0xf9 0xffff>; opp-hz = /bits/ 64 <1992000000>; opp-microvolt = <1150000 1150000 1150000>; opp-microvolt-L0 = <1150000 1150000 1150000>; @@ -211,6 +223,28 @@ opp-microvolt-L3 = <1100000 1100000 1150000>; clock-latency-ns = <40000>; }; + + /* RK3568J cpu OPPs */ + opp-j-1008000000 { + opp-supported-hw = <0x04 0xffff>; + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <850000 850000 1150000>; + clock-latency-ns = <40000>; + }; + opp-j-1416000000 { + opp-supported-hw = <0x04 0xffff>; + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <900000 900000 1150000>; + clock-latency-ns = <40000>; + }; + + /* RK3568M cpu OPPs */ + opp-m-1608000000 { + opp-supported-hw = <0x02 0xffff>; + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <1000000 1000000 1150000>; + clock-latency-ns = <40000>; + }; }; arm-pmu { @@ -309,6 +343,12 @@ }; }; + mipi_csi2: mipi-csi2 { + compatible = "rockchip,rk3568-mipi-csi2"; + rockchip,hw = <&mipi_csi2_hw>; + status = "disabled"; + }; + mpp_srv: mpp-srv { compatible = "rockchip,mpp-service"; rockchip,taskqueue-count = <6>; @@ -1106,8 +1146,11 @@ compatible = "operating-points-v2"; mbist-vmin = <825000 900000 950000>; - nvmem-cells = <&npu_leakage>, <&core_pvtm>, <&mbist_vmin>, <&npu_opp_info>; - nvmem-cell-names = "leakage", "pvtm", "mbist-vmin", "opp-info"; + nvmem-cells = <&npu_leakage>, <&core_pvtm>, <&mbist_vmin>, <&npu_opp_info>, + <&specification_serial_number>; + nvmem-cell-names = "leakage", "pvtm", "mbist-vmin", "opp-info", + "specification_serial_number"; + rockchip,supported-hw; rockchip,max-volt = <1000000>; rockchip,temp-hysteresis = <5000>; rockchip,low-temp = <0>; @@ -1123,23 +1166,29 @@ >; rockchip,pvtm-ch = <0 5>; + /* RK3568 && RK3568M npu OPPs */ opp-200000000 { + opp-supported-hw = <0xfb 0xffff>; opp-hz = /bits/ 64 <200000000>; opp-microvolt = <850000 850000 1000000>; }; opp-300000000 { + opp-supported-hw = <0xfb 0xffff>; opp-hz = /bits/ 64 <297000000>; opp-microvolt = <850000 850000 1000000>; }; opp-400000000 { + opp-supported-hw = <0xfb 0xffff>; opp-hz = /bits/ 64 <400000000>; opp-microvolt = <850000 850000 1000000>; }; opp-600000000 { + opp-supported-hw = <0xfb 0xffff>; opp-hz = /bits/ 64 <600000000>; opp-microvolt = <850000 850000 1000000>; }; opp-700000000 { + opp-supported-hw = <0xfb 0xffff>; opp-hz = /bits/ 64 <700000000>; opp-microvolt = <875000 875000 1000000>; opp-microvolt-L0 = <875000 875000 1000000>; @@ -1148,6 +1197,7 @@ opp-microvolt-L3 = <850000 850000 1000000>; }; opp-800000000 { + opp-supported-hw = <0xfb 0xffff>; opp-hz = /bits/ 64 <800000000>; opp-microvolt = <925000 925000 1000000>; opp-microvolt-L0 = <925000 925000 1000000>; @@ -1156,6 +1206,7 @@ opp-microvolt-L3 = <875000 875000 1000000>; }; opp-900000000 { + opp-supported-hw = <0xf9 0xffff>; opp-hz = /bits/ 64 <900000000>; opp-microvolt = <975000 975000 1000000>; opp-microvolt-L0 = <975000 975000 1000000>; @@ -1164,6 +1215,7 @@ opp-microvolt-L3 = <900000 900000 1000000>; }; opp-1000000000 { + opp-supported-hw = <0xf9 0xffff>; opp-hz = /bits/ 64 <1000000000>; opp-microvolt = <1000000 1000000 1000000>; opp-microvolt-L0 = <1000000 1000000 1000000>; @@ -1172,6 +1224,20 @@ opp-microvolt-L3 = <925000 925000 1000000>; status = "disabled"; }; + + /* RK3568J npu OPPs */ + opp-j-600000000 { + opp-supported-hw = <0x04 0xffff>; + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <900000 900000 1000000>; + }; + + /* RK3568M npu OPPs */ + opp-m-900000000 { + opp-supported-hw = <0x02 0xffff>; + opp-hz = /bits/ 64 <900000000>; + opp-microvolt = <925000 925000 1000000>; + }; }; bus_npu: bus-npu { @@ -1262,8 +1328,11 @@ compatible = "operating-points-v2"; mbist-vmin = <825000 900000 950000>; - nvmem-cells = <&gpu_leakage>, <&core_pvtm>, <&mbist_vmin>, <&gpu_opp_info>; - nvmem-cell-names = "leakage", "pvtm", "mbist-vmin", "opp-info"; + nvmem-cells = <&gpu_leakage>, <&core_pvtm>, <&mbist_vmin>, <&gpu_opp_info>, + <&specification_serial_number>; + nvmem-cell-names = "leakage", "pvtm", "mbist-vmin", "opp-info", + "specification_serial_number"; + rockchip,supported-hw; rockchip,max-volt = <1000000>; rockchip,temp-hysteresis = <5000>; rockchip,low-temp = <0>; @@ -1279,19 +1348,24 @@ >; rockchip,pvtm-ch = <0 5>; + /* RK3568 && RK3568M gpu OPPs */ opp-200000000 { + opp-supported-hw = <0xfb 0xffff>; opp-hz = /bits/ 64 <200000000>; opp-microvolt = <850000 850000 1000000>; }; opp-300000000 { + opp-supported-hw = <0xfb 0xffff>; opp-hz = /bits/ 64 <300000000>; opp-microvolt = <850000 850000 1000000>; }; opp-400000000 { + opp-supported-hw = <0xfb 0xffff>; opp-hz = /bits/ 64 <400000000>; opp-microvolt = <850000 850000 1000000>; }; opp-600000000 { + opp-supported-hw = <0xfb 0xffff>; opp-hz = /bits/ 64 <600000000>; opp-microvolt = <900000 900000 1000000>; opp-microvolt-L0 = <900000 900000 1000000>; @@ -1300,6 +1374,7 @@ opp-microvolt-L3 = <850000 850000 1000000>; }; opp-700000000 { + opp-supported-hw = <0xfb 0xffff>; opp-hz = /bits/ 64 <700000000>; opp-microvolt = <950000 950000 1000000>; opp-microvolt-L0 = <950000 950000 1000000>; @@ -1308,6 +1383,7 @@ opp-microvolt-L3 = <875000 875000 1000000>; }; opp-800000000 { + opp-supported-hw = <0xf9 0xffff>; opp-hz = /bits/ 64 <800000000>; opp-microvolt = <1000000 1000000 1000000>; opp-microvolt-L0 = <1000000 1000000 1000000>; @@ -1315,6 +1391,21 @@ opp-microvolt-L2 = <950000 950000 1000000>; opp-microvolt-L3 = <925000 925000 1000000>; }; + + /* RK3568J gpu OPPs */ + opp-j-600000000 { + opp-supported-hw = <0x04 0xffff>; + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <900000 900000 1000000>; + }; + + /* RK3568M gpu OPPs */ + opp-m-800000000 { + opp-supported-hw = <0x02 0xffff>; + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <950000 950000 1000000>; + }; + }; pvtm@fde80000 { @@ -1642,8 +1733,8 @@ status = "disabled"; }; - mipi_csi2: mipi-csi2@fdfb0000 { - compatible = "rockchip,rk3568-mipi-csi2"; + mipi_csi2_hw: mipi-csi2-hw@fdfb0000 { + compatible = "rockchip,rk3568-mipi-csi2-hw"; reg = <0x0 0xfdfb0000 0x0 0x10000>; reg-names = "csihost_regs"; interrupts = , @@ -2326,8 +2417,11 @@ compatible = "operating-points-v2"; mbist-vmin = <825000 900000 950000>; - nvmem-cells = <&log_leakage>, <&core_pvtm>, <&mbist_vmin>, <&dmc_opp_info>; - nvmem-cell-names = "leakage", "pvtm", "mbist-vmin", "opp-info"; + nvmem-cells = <&log_leakage>, <&core_pvtm>, <&mbist_vmin>, <&dmc_opp_info>, + <&specification_serial_number>; + nvmem-cell-names = "leakage", "pvtm", "mbist-vmin", "opp-info", + "specification_serial_number"; + rockchip,supported-hw; rockchip,max-volt = <1000000>; rockchip,temp-hysteresis = <5000>; rockchip,low-temp = <0>; @@ -2345,12 +2439,21 @@ >; rockchip,pvtm-ch = <0 5>; + /* RK3568 dmc OPPs */ opp-1560000000 { + opp-supported-hw = <0xf9 0xffff>; opp-hz = /bits/ 64 <1560000000>; opp-microvolt = <900000 900000 1000000>; opp-microvolt-L0 = <900000 900000 1000000>; opp-microvolt-L1 = <875000 875000 1000000>; }; + + /* RK3568J/M dmc OPPs */ + opp-j-m-1560000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <1560000000>; + opp-microvolt = <875000 875000 1000000>; + }; }; pcie2x1: pcie@fe260000 { @@ -2682,6 +2785,10 @@ cpu_code: cpu-code@2 { reg = <0x02 0x2>; }; + specification_serial_number: specification-serial-number@7 { + reg = <0x07 0x1>; + bits = <0 5>; + }; otp_cpu_version: cpu-version@8 { reg = <0x08 0x1>; bits = <3 3>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-adsp-audio-s66.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-adsp-audio-s66.dtsi new file mode 100644 index 000000000000..5609397a2442 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-adsp-audio-s66.dtsi @@ -0,0 +1,99 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +/ { + dummy_codec: dummy-codec { + compatible = "rockchip,dummy-codec"; + #sound-dai-cells = <0>; + status = "okay"; + }; + + sound0 { + compatible = "simple-audio-card"; + simple-audio-card,name = "rockchip,tdm"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,bitclock-master = <&codec_master>; + simple-audio-card,frame-master = <&codec_master>; + status = "okay"; + + simple-audio-card,cpu { + sound-dai = <&i2s1_8ch>; + }; + codec_master: simple-audio-card,codec { + sound-dai = <&dummy_codec>; + }; + }; + + bt_codec: bt-codec { + compatible = "delta,dfbmcs320"; + #sound-dai-cells = <1>; + status = "okay"; + }; + + sound1 { + compatible = "simple-audio-card"; + simple-audio-card,name = "rockchip,bt"; + simple-audio-card,format = "dsp_a"; + simple-audio-card,bitclock-inversion = <1>; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,cpu { + sound-dai = <&i2s3_2ch>; + }; + simple-audio-card,codec { + sound-dai = <&bt_codec 1>; + }; + }; +}; + +&i2s1_8ch { + pinctrl-0 = <&i2s1m0_lrck + &i2s1m0_sclk + &i2s1m0_sdi0 + &i2s1m0_sdi1 + &i2s1m0_sdo0 + &i2s1m0_sdo1 + &i2s1m0_sdo2>; + i2s-lrck-gpio = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; + tdm-fsync-gpio = <&gpio4 RK_PA0 GPIO_ACTIVE_HIGH>; + rockchip,tdm-multi-lanes; + rockchip,tdm-tx-lanes = <3>; + rockchip,tdm-rx-lanes = <2>; + rockchip,clk-trcm = <1>; + status = "okay"; +}; + +&i2s3_2ch { + assigned-clocks = <&cru CLK_I2S3_2CH>; + assigned-clock-parents = <&mclkin_i2s3>; + pinctrl-0 = <&i2s3_sdi + &i2s3_sdo + &i2s3_mclk>; + status = "okay"; +}; + +&mclkin_i2s3 { + clock-frequency = <12288000>; +}; + +&spi3 { + status = "okay"; + assigned-clocks = <&cru CLK_SPI3>; + assigned-clock-rates = <200000000>; + num-cs = <2>; + pinctrl-0 = <&spi3m2_cs0 + &spi3m2_cs1 + &spi3m2_pins>; + + flash: is25lp032@1 { + compatible = "issi,is25lp032", "jedec,spi-nor"; + reg = <1>; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <5000000>; + m25p,fast-read; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v21.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v21.dtsi index e08c45896e4c..b6c622fa9a75 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v21.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v21.dtsi @@ -52,10 +52,11 @@ vcc3v3_pcie_wifi: vcc3v3-pcie-wifi { compatible = "regulator-fixed"; regulator-name = "vcc3v3_pcie_wifi"; + regulator-always-on; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; enable-active-high; - //gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_HIGH>; + gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_HIGH>; startup-delay-us = <5000>; vin-supply = <&vcc_3v3_s0>; }; @@ -123,7 +124,7 @@ compatible = "wlan-platdata"; wifi_chip_type = "ap6398s"; pinctrl-names = "default"; - pinctrl-0 = <&wifi_poweren_gpio>, <&wifi_host_wake_irq>; + pinctrl-0 = <&wifi_host_wake_irq>; WIFI,host_wake_irq = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; WIFI,poweren_gpio = <&gpio3 RK_PA3 GPIO_ACTIVE_HIGH>; status = "okay"; @@ -287,9 +288,6 @@ rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>; }; - wifi_poweren_gpio: wifi-power-gpio { - rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_down>; - }; }; rk3308 { diff --git a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-maxim-cameras-s66.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-maxim-cameras-s66.dtsi new file mode 100644 index 000000000000..566c9d00095b --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-maxim-cameras-s66.dtsi @@ -0,0 +1,319 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +/ { + max96712_osc: max96712-oscillator { + compatible = "fixed-clock"; + #clock-cells = <1>; + clock-frequency = <25000000>; + clock-output-names = "max96712-osc"; + }; + + max96722_osc: max96722-oscillator { + compatible = "fixed-clock"; + #clock-cells = <1>; + clock-frequency = <25000000>; + clock-output-names = "max96722-osc"; + }; +}; + +/** + * ============================================================================ + * Inno DPHY0: full mode + * ============================================================================ + */ +&csi2_dphy0_hw { + status = "okay"; +}; + +&csi2_dphy0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_dphy0_in_max96712: endpoint@1 { + reg = <1>; + remote-endpoint = <&max96712_out>; + data-lanes = <1 2 3 4>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi2_csi2_input>; + }; + }; + }; +}; + +&mipi2_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi2_in>; + }; + }; + }; +}; + +&rkcif_mipi_lvds2 { + status = "okay"; + /* parameters for do cif reset detecting: + * index0: monitor mode, + 0 for idle, + 1 for continue, + 2 for trigger, + 3 for hotplug (for nextchip) + * index1: the frame id to start timer, + min is 2 + * index2: frame num of monitoring cycle + * index3: err time for keep monitoring + after finding out err (ms) + * index4: csi2 err reference val for resetting + */ + rockchip,cif-monitor = <3 2 1 1000 5>; + + port { + cif_mipi2_in: endpoint { + remote-endpoint = <&mipi2_csi2_output>; + }; + }; +}; + +/** + * ============================================================================ + * Inno DPHY1: full mode + * ============================================================================ + */ +&csi2_dphy1_hw { + status = "okay"; +}; + +&csi2_dphy3 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_dphy3_in_max96722: endpoint@1 { + reg = <1>; + remote-endpoint = <&max96722_out>; + data-lanes = <1 2 3 4>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy3_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi4_csi2_input>; + }; + }; + }; +}; + +&mipi4_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi4_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy3_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi4_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi4_in>; + }; + }; + }; +}; + +&rkcif_mipi_lvds4 { + status = "okay"; + /* parameters for do cif reset detecting: + * index0: monitor mode, + 0 for idle, + 1 for continue, + 2 for trigger, + 3 for hotplug (for nextchip) + * index1: the frame id to start timer, + min is 2 + * index2: frame num of monitoring cycle + * index3: err time for keep monitoring + after finding out err (ms) + * index4: csi2 err reference val for resetting + */ + rockchip,cif-monitor = <3 2 1 1000 5>; + + port { + cif_mipi4_in: endpoint { + remote-endpoint = <&mipi4_csi2_output>; + }; + }; +}; + +/** + * ============================================================================= + * Common + * ============================================================================= + */ +&rkcif { + status = "okay"; + rockchip,android-usb-camerahal-enable; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&i2c2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2m4_xfer>; + clock-frequency = <400000>; + + // AVM Camera x4 + max96712: max96712@29 { + compatible = "maxim,max96712"; + status = "okay"; + reg = <0x29>; + clock-names = "xvclk"; + clocks = <&max96712_osc 0>; + pinctrl-names = "default"; + pinctrl-0 = <&max96712_power>, <&max96712_errb>, <&max96712_lock>; + power-domains = <&power RK3588_PD_VI>; + rockchip,grf = <&sys_grf>; + power-gpios = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; + lock-gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_HIGH>; + link-mask = <0x0F>; + auto-init-deskew-mask = <0x3>; + frame-sync-period = <0>; + link-rx-rate = <0>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "max96712"; + rockchip,camera-module-lens-name = "max96712"; + + port { + max96712_out: endpoint { + remote-endpoint = <&mipi_dphy0_in_max96712>; + data-lanes = <1 2 3 4>; + }; + }; + }; + + // DMS Camera x1 + OMS Camera x3 + max96722: max96722@6b { + compatible = "maxim,max96722"; + status = "okay"; + reg = <0x6b>; + clock-names = "xvclk"; + clocks = <&max96722_osc 0>; + pinctrl-names = "default"; + pinctrl-0 = <&max96722_power>, <&max96722_errb>, <&max96722_lock>; + power-domains = <&power RK3588_PD_VI>; + rockchip,grf = <&sys_grf>; + power-gpios = <&gpio1 RK_PC7 GPIO_ACTIVE_HIGH>; + lock-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; + link-mask = <0x33>; + auto-init-deskew-mask = <0x3>; + frame-sync-period = <0>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "max96722"; + rockchip,camera-module-lens-name = "max96722"; + + port { + max96722_out: endpoint { + remote-endpoint = <&mipi_dphy3_in_max96722>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&pinctrl { + maxim-cameras { + max96712_power: max96712-power { + rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + max96712_errb: max96712-errb { + rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + max96712_lock: max96712-lock { + rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + max96722_power: max96722-power { + rockchip,pins = <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + max96722_errb: max96722-errb { + rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + max96722_lock: max96722-lock { + rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-maxim-serdes-display-s66.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-maxim-serdes-display-s66.dtsi new file mode 100644 index 000000000000..588e5695bf11 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-maxim-serdes-display-s66.dtsi @@ -0,0 +1,564 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + */ + +#include + +/ { + aliases { + pinctrl0 = &pinctrl; + }; + + backlight { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + i2c8_max96755f_backlight: backlight@0 { + compatible = "pwm-backlight"; + reg = <0>; + pwms = <&pwm0 0 1000000 0>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + }; + + i2c8_max96745_1_backlight: backlight@1 { + compatible = "pwm-backlight"; + reg = <0>; + pwms = <&pwm1 0 1000000 0>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + }; + + i2c8_max96745_2_backlight: backlight@2 { + compatible = "pwm-backlight"; + reg = <0>; + pwms = <&pwm7 0 1000000 0>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + }; + }; +}; + +&dp0 { + //split-mode; + force-hpd; + status = "disabled"; +}; + +&dp0_in_vp0 { + status = "okay"; +}; + +&usbdp_phy0 { + rockchip,dp-lane-mux = <0 1 2 3>; + status = "okay"; +}; + +&usbdp_phy0_dp { + status = "okay"; +}; + +&route_dp0 { + connect = <&vp0_out_dp0>; + status = "disabled"; +}; + +&dp1 { + force-hpd; + status = "disabled"; +}; + +&usbdp_phy1 { + //rockchip,dp-lane-mux = <0 1 2 3>; + status = "disabled"; +}; + +&usbdp_phy1_dp { + status = "disabled"; +}; + +&dsi0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + dsi0_out: endpoint { + remote-endpoint = <&i2c8_max96755f_in>; + }; + }; + }; +}; + +&mipi_dcphy0 { + status = "okay"; +}; + +&dsi0_in_vp2 { + status = "okay"; +}; + +&route_dsi0 { + connect = <&vp2_out_dsi0>; + status = "disabled"; +}; + +&dsi1 { + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + dsi1_out: endpoint { + //remote-endpoint = <&i2c6_max96755f_in>; + }; + }; + }; +}; + +&mipi_dcphy1 { + status = "okay"; +}; + +&dsi1_in_vp3 { + status = "okay"; +}; + +&route_dsi1 { + connect = <&vp3_out_dsi1>; + status = "disabled"; +}; + +&edp0 { + split-mode; + force-hpd; + status = "disabled"; +}; + +&edp0_out { + link-frequencies = /bits/ 64 <2700000000>; + remote-endpoint = <&i2c8_max96745_1_in>; +}; + +&hdptxphy0 { + status = "okay"; +}; + +&edp0_in_vp1 { + status = "okay"; +}; + +&route_edp0 { + connect = <&vp1_out_edp0>; + status = "disabled"; +}; + +&edp1 { + force-hpd; + status = "disabled"; +}; + +&edp1_out { + link-frequencies = /bits/ 64 <2700000000>; + remote-endpoint = <&i2c8_max96745_2_in>; +}; + +&hdptxphy1 { + status = "okay"; +}; + +&hdmi0 { + status = "disabled"; +}; + +&hdmi1 { + status = "disabled"; +}; + +&hdptxphy_hdmi0 { + status = "disabled"; +}; + +&hdptxphy_hdmi1 { + status = "disabled"; +}; + +&i2c8 { + pinctrl-0 = <&i2c8m4_xfer>; + clock-frequency = <400000>; + status = "okay"; + + max96755f@62 { + compatible = "maxim,max96755f"; + reg = <0x62>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c8_ser1_lock_pins>, <&i2c8_ser1_pwdnb_pins>; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl { + compatible = "maxim,max96755f-pinctrl"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c8_max96755f_pinctrl_hog>; + + i2c8_max96755f_pinctrl_hog: hog { + i2c { + groups = "I2C"; + function = "I2C"; + }; + }; + + i2c8_max96755f_panel_pins: panel-pins { + bl-pwm { + pins = "MFP7"; + function = "GPIO_TX_0"; + }; + + tp-int { + pins = "MFP8"; + function = "GPIO_RX_2"; + }; + }; + }; + + bridge { + compatible = "maxim,max96755f-bridge"; + lock-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; + bridge_dual_link; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2c8_max96755f_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + + i2c8_max96755f_out: endpoint { + remote-endpoint = <&i2c8_max96755f_panel_in>; + }; + }; + }; + }; + + gmsl@0 { + reg = <0>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + + ts@30 { + compatible = "gac,gac_ts"; + reg = <0x30>; + pinctrl-names = "pmx_ts_active","pmx_ts_suspend"; + pinctrl-0 = <&touch_pin>; + pinctrl-1 = <&touch_pin>; + interrupt-parent = <&gpio1>; + interrupts = ; + gac,max_x = <2560>; + gac,max_y = <1440>; + }; + + panel@48 { + compatible = "boe,ae146m1t-l10"; + reg = <0x48>; + backlight = <&i2c8_max96755f_backlight>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c8_max96755f_panel_pins>; + panel_dual_link; + + panel-timing { + clock-frequency = <303000000>; + hactive = <2560>; + vactive = <1440>; + hfront-porch = <122>; + hsync-len = <60>; + hback-porch = <60>; + vfront-porch = <340>; + vsync-len = <2>; + vback-porch = <20>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + + port { + i2c8_max96755f_panel_in: endpoint { + remote-endpoint = <&i2c8_max96755f_out>; + }; + }; + }; + }; + }; +}; + +&i2c8 { + status = "okay"; + + max96745@42 { + compatible = "maxim,max96745"; + reg = <0x42>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c8_ser2_lock_pins>; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl { + compatible = "maxim,max96745-pinctrl"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c8_max96745_1_pinctrl_hog>; + + i2c8_max96745_1_pinctrl_hog: hog { + i2c { + groups = "I2C"; + function = "I2C"; + }; + }; + + i2c8_max96745_1_panel_pins: panel-pins { + bl-pwm { + pins = "MFP11"; + function = "GPIO_TX_A_0"; + }; + }; + }; + + bridge { + compatible = "maxim,max96745-bridge"; + lock-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2c8_max96745_1_in: endpoint { + remote-endpoint = <&edp0_out>; + }; + }; + + port@1 { + reg = <1>; + + i2c8_max96745_1_out: endpoint { + remote-endpoint = <&i2c8_max96745_1_panel_in>; + }; + }; + }; + }; + + gmsl@0 { + reg = <0>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + + panel@48 { + compatible = "boe,av156fht-l83"; + reg = <0x48>; + backlight = <&i2c8_max96745_1_backlight>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c8_max96745_1_panel_pins>; + + panel-timing { + clock-frequency = <148500000>; + hactive = <1920>; + vactive = <1080>; + hfront-porch = <20>; + hsync-len = <20>; + hback-porch = <20>; + vfront-porch = <250>; + vsync-len = <2>; + vback-porch = <8>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + + port { + i2c8_max96745_1_panel_in: endpoint { + remote-endpoint = <&i2c8_max96745_1_out>; + }; + }; + }; + }; + }; +}; + +&i2c8 { + status = "okay"; + + max96745@60 { + compatible = "maxim,max96745"; + reg = <0x60>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c8_ser3_lock_pins>; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl { + compatible = "maxim,max96745-pinctrl"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c8_max96745_2_pinctrl_hog>; + + i2c8_max96745_2_pinctrl_hog: hog { + i2c { + groups = "I2C"; + function = "I2C"; + }; + }; + + i2c8_max96745_2_panel_pins: panel-pins { + bl-pwm { + pins = "MFP11"; + function = "GPIO_TX_A_0"; + }; + }; + }; + + bridge { + compatible = "maxim,max96745-bridge"; + lock-gpios = <&gpio4 RK_PC4 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2c8_max96745_2_in: endpoint { + remote-endpoint = <&edp1_out>; + }; + }; + + port@1 { + reg = <1>; + + i2c8_max96745_2_out: endpoint { + remote-endpoint = <&i2c8_max96745_2_panel_in>; + }; + }; + }; + }; + + gmsl@0 { + reg = <0>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + + panel@48 { + compatible = "boe,av156fht-l83"; + reg = <0x48>; + backlight = <&i2c8_max96745_2_backlight>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c8_max96745_2_panel_pins>; + + panel-timing { + clock-frequency = <148500000>; + hactive = <1920>; + vactive = <1080>; + hfront-porch = <20>; + hsync-len = <20>; + hback-porch = <20>; + vfront-porch = <250>; + vsync-len = <2>; + vback-porch = <8>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + + port { + i2c8_max96745_2_panel_in: endpoint { + remote-endpoint = <&i2c8_max96745_2_out>; + }; + }; + }; + }; + }; +}; + +&pinctrl { + serdes { + i2c8_ser1_lock_pins: i2c8-ser1-lock-pins { + rockchip,pins = + <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + i2c8_ser2_lock_pins: i2c8-ser2-lock-pins { + rockchip,pins = + <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + i2c8_ser3_lock_pins: i2c8-ser3-lock-pins { + rockchip,pins = + <4 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + i2c8_ser1_errb_pins: i2c8-ser1-errb-pins { + rockchip,pins = + <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + i2c8_ser2_errb_pins: i2c8-ser2-errb-pins { + rockchip,pins = + <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + i2c8_ser3_errb_pins: i2c8-ser3-errb-pins { + rockchip,pins = + <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + i2c8_ser1_pwdnb_pins: i2c8-ser1-pwdnb-pins { + rockchip,pins = + <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + touch { + touch_pin: touch-pin { + rockchip,pins = + <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pwm0 { + pinctrl-0 = <&pwm0m2_pins>; + status = "okay"; +}; + +&pwm1 { + pinctrl-0 = <&pwm1m1_pins>; + status = "okay"; +}; + +&pwm7 { + pinctrl-0 = <&pwm7m3_pins>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-s66-v10.dts b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-s66-v10.dts new file mode 100644 index 000000000000..e27ee5107455 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-s66-v10.dts @@ -0,0 +1,89 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3588-vehicle-s66-v10.dtsi" +#include "rk3588-vehicle-adsp-audio-s66.dtsi" +#include "rk3588-vehicle-maxim-serdes-display-s66.dtsi" +#include "rk3588-vehicle-maxim-cameras-s66.dtsi" +#include "rk3588-android.dtsi" + +/ { + model = "Rockchip RK3588 VEHICLE S66 Board V10"; + compatible = "rockchip,rk3588-vehicle-s66-v10", "rockchip,rk3588"; +}; + +&rockchip_suspend { + rockchip,sleep-mode-config = < + (0 + | RKPM_SLP_ARMOFF_DDRPD + | RKPM_SLP_PMU_PMUALIVE_32K + | RKPM_SLP_PMU_DIS_OSC + | RKPM_SLP_32K_EXT + ) + >; + rockchip,wakeup-config = < + (0 + | RKPM_GPIO_WKUP_EN + ) + >; + status = "okay"; +}; + +&vdd_log_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <800000>; + }; +}; + +&vcc_3v3_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; +}; + +&vcc_1v8_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; +}; + +&vccio_sd_s0 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; +}; + +&vdd_0v75_hdmi_edp_s0 { + regulator-min-microvolt = <837500>; + regulator-max-microvolt = <837500>; +}; + +&vdd_cpu_big1_mem_s0 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; +}; + +&vdd_cpu_big0_mem_s0 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; +}; + +&vdd_cpu_lit_mem_s0 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; +}; + +&vdd_gpu_mem_s0 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-s66-v10.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-s66-v10.dtsi new file mode 100644 index 000000000000..6cd0f027bacc --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-s66-v10.dtsi @@ -0,0 +1,252 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +#include "rk3588m.dtsi" +#include "rk3588-vehicle-s66.dtsi" +#include "rk3588-rk806-dual.dtsi" +/ { + pcie20_avdd0v85: pcie20-avdd0v85 { + compatible = "regulator-fixed"; + regulator-name = "pcie20_avdd0v85"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + vin-supply = <&vdd_0v85_s0>; + }; + + pcie20_avdd1v8: pcie20-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "pcie20_avdd1v8"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + pcie30_avdd0v75: pcie30-avdd0v75 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v75"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + vin-supply = <&avdd_0v75_s0>; + }; + + pcie30_avdd1v8: pcie30-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + vcc3v3_pcie_wifi: vcc3v3-pcie-wifi { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie_wifi"; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + vin-supply = <&vcc_3v3_s0>; + }; + + vcc5v0_host: vcc5v0-host { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + //gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_usb>; + //pinctrl-names = "default"; + //pinctrl-0 = <&vcc5v0_host_en>; + //TODO: should powered by MCU + }; + + wireless_bluetooth: wireless-bluetooth { + compatible = "bluetooth-platdata"; + BT,reset_gpio = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless_wlan: wireless-wlan { + compatible = "wlan-platdata"; + wifi_chip_type = "ap6398s"; + WIFI,poweren_gpio = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy1_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&gmac0 { + /* Use rgmii-rxid mode to disable rx delay inside Soc */ + phy-mode = "rgmii-rxid"; + clock_in_out = "output"; + snps,reset-gpio = <&gpio2 RK_PC5 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus>; + tx_delay = <0x43>; + //rx_delay = <0x3f>; + phy-handle = <&rgmii_phy>; + status = "okay"; +}; + +&i2c3 { + status = "okay"; + + iam20680_acc: acc@69 { + compatible = "iam20680_acc"; + reg = <0x69>; + irq-gpio = <&gpio1 RK_PC2 IRQ_TYPE_LEVEL_LOW>; + irq_enable = <1>; + poll_delay_ms = <30>; + type = ; + layout = <1>; + }; + + iam20680_gyro: gyro@69 { + compatible = "iam20680_gyro"; + reg = <0x69>; + irq_enable = <0>; + poll_delay_ms = <30>; + type = ; + layout = <1>; + }; + + //todo, add mfi +}; + +&i2c4 { + status = "okay"; + pinctrl-0 = <&i2c4m0_xfer>; + //todo, add LT9211 +}; + +&mdio0 { + rgmii_phy: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + }; +}; + +&pcie2x1l0 { + status = "disabled"; +}; + +&pcie2x1l1 { + status = "disabled"; +}; + +&pcie2x1l2 { + reset-gpios = <&gpio4 RK_PC1 GPIO_ACTIVE_HIGH>; + rockchip,skip-scan-in-resume; + rockchip,perst-inactive-ms = <500>; + vpcie3v3-supply = <&vcc3v3_pcie_wifi>; + status = "okay"; +}; + +&pcie30phy { + rockchip,pcie30-phymode = ; + status = "disabled"; +}; + +&pcie3x4 { + num-lanes = <1>; + status = "disabled"; +}; + +&sata0 { + status = "disabled"; +}; + +&sdmmc { + status = "disabled"; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1m1_xfer &uart1m1_ctsn &uart1m1_rtsn>; +}; + +&u2phy1_otg { + phy-supply = <&vcc5v0_host>; +}; + +&u2phy2_host { + phy-supply = <&vcc5v0_host>; +}; + +&u2phy3_host { + phy-supply = <&vcc5v0_host>; +}; + +&usbdp_phy0 { + rockchip,dp-lane-mux = <2 3>; + status = "okay"; +}; + +&usbdp_phy0_dp { + status = "okay"; +}; + +&usbdp_phy0_u3 { + status = "okay"; +}; + +&usbdp_phy1 { + rockchip,dp-lane-mux = <3 2 1 0>; + status = "disabled"; +}; + +&usbdp_phy1_dp { + status = "disabled"; +}; + +&usbdp_phy1_u3 { + maximum-speed = "high-speed"; + status = "okay"; +}; + +&usbdrd_dwc3_0 { + dr_mode = "peripheral"; + maximum-speed = "high-speed"; + extcon = <&u2phy0>; + status = "okay"; +}; + +&usbdrd_dwc3_1 { + dr_mode = "host"; + maximum-speed = "high-speed"; + snps,dis_u2_susphy_quirk; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-s66.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-s66.dtsi new file mode 100644 index 000000000000..33e9186ca2e0 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-s66.dtsi @@ -0,0 +1,434 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include +#include +#include +#include +#include +/ { + backlight: backlight { + compatible = "pwm-backlight"; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + test-power { + status = "okay"; + }; + + vcc12v_dcin: vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usbdcin: vcc5v0-usbdcin { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usbdcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usb: vcc5v0-usb { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usbdcin>; + }; +}; + +&av1d_mmu { + status = "okay"; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; + mem-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; + mem-supply = <&vdd_cpu_big1_s0>; +}; + +&gpu { + mali-supply = <&vdd_gpu_s0>; + mem-supply = <&vdd_gpu_s0>; + status = "okay"; +}; + +&i2s0_8ch { + status = "disabled"; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&jpege_ccu { + status = "okay"; +}; + +&jpege0 { + status = "okay"; +}; + +&jpege0_mmu { + status = "okay"; +}; + +&jpege1 { + status = "okay"; +}; + +&jpege1_mmu { + status = "okay"; +}; + +&jpege2 { + status = "okay"; +}; + +&jpege2_mmu { + status = "okay"; +}; + +&jpege3 { + status = "okay"; +}; + +&jpege3_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&rga3_core0 { + status = "okay"; +}; + +&rga3_0_mmu { + status = "okay"; +}; + +&rga3_core1 { + status = "okay"; +}; + +&rga3_1_mmu { + status = "okay"; +}; + +&rga2 { + status = "okay"; +}; + +&rknpu { + rknpu-supply = <&vdd_npu_s0>; + mem-supply = <&vdd_npu_s0>; + status = "okay"; +}; + +&rknpu_mmu { + status = "okay"; +}; + +&rkvdec_ccu { + status = "okay"; +}; + +&rkvdec0 { + status = "okay"; +}; + +&rkvdec0_mmu { + status = "okay"; +}; + +&rkvdec1 { + status = "okay"; +}; + +&rkvdec1_mmu { + status = "okay"; +}; + +&rkvenc_ccu { + status = "okay"; +}; + +&rkvenc0 { + status = "okay"; +}; + +&rkvenc0_mmu { + status = "okay"; +}; + +&rkvenc1 { + status = "okay"; +}; + +&rkvenc1_mmu { + status = "okay"; +}; + +&rockchip_suspend { + status = "okay"; + rockchip,sleep-debug-en = <1>; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcc_1v8_s0>; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + status = "okay"; +}; + +&sdmmc { + max-frequency = <150000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vqmmc-supply = <&vccio_sd_s0>; + status = "disabled"; +}; + +&tsadc { + status = "okay"; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy1 { + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + +&u2phy1_otg { + rockchip,sel-pipe-phystatus; + status = "okay"; +}; + +&u2phy2_host { + status = "okay"; +}; + +&u2phy3_host { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdp_phy0 { + rockchip,dp-lane-mux = <2 3>; + status = "okay"; +}; + +&usbdp_phy0_dp { + status = "disabled"; +}; + +&usbdp_phy0_u3 { + status = "okay"; +}; + +&usbdp_phy1 { + status = "okay"; +}; + +&usbdp_phy1_dp { + status = "okay"; +}; + +&usbdp_phy1_u3 { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + dr_mode = "otg"; + extcon=<&u2phy0>; + status = "okay"; +}; + +&usbhost3_0 { + status = "okay"; +}; + +&usbhost_dwc3_0 { + status = "okay"; +}; + +&usbdrd3_1 { + status = "okay"; +}; + +&usbdrd_dwc3_1 { + dr_mode = "host"; + maximum-speed = "high-speed"; + phys = <&u2phy1_otg>; + phy-names = "usb2-phy"; + snps,dis_u2_susphy_quirk; + status = "okay"; +}; + +&vdpu { + status = "okay"; +}; + +&vdpu_mmu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +/* vp0 & vp1 splice for 8K output */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0)>; + rockchip,primary-plane = ; +}; + +&vp1 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1)>; + rockchip,primary-plane = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER2 | 1 << ROCKCHIP_VOP2_ESMART2)>; + rockchip,primary-plane = ; +}; + +&vp3 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER3 | 1 << ROCKCHIP_VOP2_ESMART3)>; + rockchip,primary-plane = ; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-serdes-display-v20.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-serdes-display-v20.dtsi index b458efd4ad9a..dabfc3d853aa 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-serdes-display-v20.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-serdes-display-v20.dtsi @@ -5,14 +5,6 @@ */ / { - lt7911d { - compatible = "lontium,lt7911d-fb-notifier"; - reset-gpios = <&gpio0 RK_PD2 GPIO_ACTIVE_LOW>, - <&gpio4 RK_PA7 GPIO_ACTIVE_LOW>, - <&gpio3 RK_PD4 GPIO_ACTIVE_LOW>, - <&gpio3 RK_PD2 GPIO_ACTIVE_LOW>; - }; - dsi2lvds_backlight1: dsi2lvds_backlight1 { compatible = "pwm-backlight"; brightness-levels = < @@ -1015,6 +1007,13 @@ }; }; }; + + lt7911d@2b { + compatible = "lontium,lt7911d-fb-notifier"; + reg = <0x2b>; + reset-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_LOW>; + status = "okay"; + }; }; &i2c5 { @@ -1206,6 +1205,13 @@ reset-gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_LOW>; ilitek,name = "ilitek_i2c"; }; + + lt7911d@2b { + compatible = "lontium,lt7911d-fb-notifier"; + reg = <0x2b>; + reset-gpios = <&gpio0 RK_PD2 GPIO_ACTIVE_LOW>; + status = "okay"; + }; }; &i2c6 { @@ -1593,6 +1599,13 @@ }; }; }; + + lt7911d@2b { + compatible = "lontium,lt7911d-fb-notifier"; + reg = <0x2b>; + reset-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_LOW>; + status = "okay"; + }; }; &i2c8 { @@ -1769,6 +1782,13 @@ }; }; }; + + lt7911d@2b { + compatible = "lontium,lt7911d-fb-notifier"; + reg = <0x2b>; + reset-gpios = <&gpio3 RK_PD2 GPIO_ACTIVE_LOW>; + status = "okay"; + }; }; &mipi_dcphy0 { @@ -1918,25 +1938,25 @@ }; &vop { - assigned-clocks = <&cru PLL_V0PLL>; - assigned-clock-rates = <1152000000>; + //assigned-clocks = <&cru PLL_V0PLL>; + //assigned-clock-rates = <1152000000>; }; - +//dp01 &vp0 { assigned-clocks = <&cru DCLK_VOP0_SRC>; - assigned-clock-parents = <&cru PLL_V0PLL>; + assigned-clock-parents = <&cru PLL_GPLL>; }; - +//edp01 &vp1 { assigned-clocks = <&cru DCLK_VOP1_SRC>; assigned-clock-parents = <&cru PLL_GPLL>; }; - +//dsi0 &vp2 { assigned-clocks = <&cru DCLK_VOP2_SRC>; assigned-clock-parents = <&cru PLL_V0PLL>; }; - +//dsi1 &vp3 { assigned-clocks = <&cru DCLK_VOP3>; assigned-clock-parents = <&cru PLL_V0PLL>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-serdes-display-v21.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-serdes-display-v21.dtsi index eb927ddb0ddf..425cfeeacb69 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-serdes-display-v21.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-serdes-display-v21.dtsi @@ -1060,7 +1060,7 @@ }; lt7911d@2b { - compatible = "lontium,lt7911d"; + compatible = "lontium,lt7911d-fb-notifier"; reg = <0x2b>; reset-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_LOW>; status = "okay"; @@ -1268,7 +1268,7 @@ }; lt7911d@2b { - compatible = "lontium,lt7911d"; + compatible = "lontium,lt7911d-fb-notifier"; reg = <0x2b>; reset-gpios = <&gpio0 RK_PD2 GPIO_ACTIVE_LOW>; status = "okay"; @@ -1686,7 +1686,7 @@ }; lt7911d@2b { - compatible = "lontium,lt7911d"; + compatible = "lontium,lt7911d-fb-notifier"; reg = <0x2b>; reset-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_LOW>; status = "okay"; @@ -1895,7 +1895,7 @@ }; lt7911d@2b { - compatible = "lontium,lt7911d"; + compatible = "lontium,lt7911d-fb-notifier"; reg = <0x2b>; reset-gpios = <&gpio3 RK_PD2 GPIO_ACTIVE_LOW>; status = "okay"; diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588.dtsi index 6011217fd644..b8e9f601e5e5 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi @@ -9,9 +9,6 @@ / { aliases { - csi2dphy3 = &csi2_dphy3; - csi2dphy4 = &csi2_dphy4; - csi2dphy5 = &csi2_dphy5; dp0 = &dp0; dp1 = &dp1; edp0 = &edp0; @@ -30,27 +27,6 @@ usbdp1 = &usbdp_phy1; }; - /* dphy1 full mode */ - csi2_dphy3: csi2-dphy3 { - compatible = "rockchip,rk3568-csi2-dphy"; - rockchip,hw = <&csi2_dphy1_hw>; - status = "disabled"; - }; - - /* dphy1 split mode 01 */ - csi2_dphy4: csi2-dphy4 { - compatible = "rockchip,rk3568-csi2-dphy"; - rockchip,hw = <&csi2_dphy1_hw>; - status = "disabled"; - }; - - /* dphy1 split mode 23 */ - csi2_dphy5: csi2-dphy5 { - compatible = "rockchip,rk3568-csi2-dphy"; - rockchip,hw = <&csi2_dphy1_hw>; - status = "disabled"; - }; - rkcif_mipi_lvds4: rkcif-mipi-lvds4 { compatible = "rockchip,rkcif-mipi-lvds"; rockchip,hw = <&rkcif>; @@ -193,34 +169,6 @@ reg = <0x0 0xfd5e4000 0x0 0x100>; }; - mipi4_csi2: mipi4-csi2@fdd50000 { - compatible = "rockchip,rk3588-mipi-csi2"; - reg = <0x0 0xfdd50000 0x0 0x10000>; - reg-names = "csihost_regs"; - interrupts = , - ; - interrupt-names = "csi-intr1", "csi-intr2"; - clocks = <&cru PCLK_CSI_HOST_4>; - clock-names = "pclk_csi2host"; - resets = <&cru SRST_P_CSI_HOST_4>; - reset-names = "srst_csihost_p"; - status = "disabled"; - }; - - mipi5_csi2: mipi5-csi2@fdd60000 { - compatible = "rockchip,rk3588-mipi-csi2"; - reg = <0x0 0xfdd60000 0x0 0x10000>; - reg-names = "csihost_regs"; - interrupts = , - ; - interrupt-names = "csi-intr1", "csi-intr2"; - clocks = <&cru PCLK_CSI_HOST_5>; - clock-names = "pclk_csi2host"; - resets = <&cru SRST_P_CSI_HOST_5>; - reset-names = "srst_csihost_p"; - status = "disabled"; - }; - spdif_tx5: spdif-tx@fddb8000 { compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; reg = <0x0 0xfddb8000 0x0 0x1000>; @@ -869,18 +817,6 @@ }; }; - csi2_dphy1_hw: csi2-dphy1-hw@fedc8000 { - compatible = "rockchip,rk3588-csi2-dphy-hw"; - reg = <0x0 0xfedc8000 0x0 0x8000>; - clocks = <&cru PCLK_CSIPHY1>; - clock-names = "pclk"; - resets = <&cru SRST_CSIPHY1>, <&cru SRST_P_CSIPHY1>; - reset-names = "srst_csiphy1", "srst_p_csiphy1"; - rockchip,grf = <&mipidphy1_grf>; - rockchip,sys_grf = <&sys_grf>; - status = "disabled"; - }; - combphy1_ps: phy@fee10000 { compatible = "rockchip,rk3588-naneng-combphy"; reg = <0x0 0xfee10000 0x0 0x100>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi index e74fd7037c3d..de509c27f3fa 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -26,6 +26,9 @@ csi2dphy0 = &csi2_dphy0; csi2dphy1 = &csi2_dphy1; csi2dphy2 = &csi2_dphy2; + csi2dphy3 = &csi2_dphy3; + csi2dphy4 = &csi2_dphy4; + csi2dphy5 = &csi2_dphy5; dsi0 = &dsi0; dsi1 = &dsi1; ethernet1 = &gmac1; @@ -1586,37 +1589,66 @@ }; csi2_dcphy0: csi2-dcphy0 { - compatible = "rockchip,rk3588-csi2-dcphy"; - phys = <&mipi_dcphy0>; - phy-names = "dcphy"; + compatible = "rockchip,rk3588-csi2-dphy"; + rockchip,hw = <&csi2_dphy0_hw>, <&csi2_dphy1_hw>; + phys = <&mipidcphy0>, <&mipidcphy1>; + phy-names = "dcphy0", "dcphy1"; status = "disabled"; }; csi2_dcphy1: csi2-dcphy1 { - compatible = "rockchip,rk3588-csi2-dcphy"; - phys = <&mipi_dcphy1>; - phy-names = "dcphy"; + compatible = "rockchip,rk3588-csi2-dphy"; + rockchip,hw = <&csi2_dphy0_hw>, <&csi2_dphy1_hw>; + phys = <&mipidcphy0>, <&mipidcphy1>; + phy-names = "dcphy0", "dcphy1"; status = "disabled"; }; - /* dphy0 full mode */ csi2_dphy0: csi2-dphy0 { - compatible = "rockchip,rk3568-csi2-dphy"; - rockchip,hw = <&csi2_dphy0_hw>; + compatible = "rockchip,rk3588-csi2-dphy"; + rockchip,hw = <&csi2_dphy0_hw>, <&csi2_dphy1_hw>; + phys = <&mipidcphy0>, <&mipidcphy1>; + phy-names = "dcphy0", "dcphy1"; status = "disabled"; }; - /* dphy0 split mode 01 */ csi2_dphy1: csi2-dphy1 { - compatible = "rockchip,rk3568-csi2-dphy"; - rockchip,hw = <&csi2_dphy0_hw>; + compatible = "rockchip,rk3588-csi2-dphy"; + rockchip,hw = <&csi2_dphy0_hw>, <&csi2_dphy1_hw>; + phys = <&mipidcphy0>, <&mipidcphy1>; + phy-names = "dcphy0", "dcphy1"; status = "disabled"; }; - /* dphy0 split mode 23 */ csi2_dphy2: csi2-dphy2 { - compatible = "rockchip,rk3568-csi2-dphy"; - rockchip,hw = <&csi2_dphy0_hw>; + compatible = "rockchip,rk3588-csi2-dphy"; + rockchip,hw = <&csi2_dphy0_hw>, <&csi2_dphy1_hw>; + phys = <&mipidcphy0>, <&mipidcphy1>; + phy-names = "dcphy0", "dcphy1"; + status = "disabled"; + }; + + csi2_dphy3: csi2-dphy3 { + compatible = "rockchip,rk3588-csi2-dphy"; + rockchip,hw = <&csi2_dphy0_hw>, <&csi2_dphy1_hw>; + phys = <&mipidcphy0>, <&mipidcphy1>; + phy-names = "dcphy0", "dcphy1"; + status = "disabled"; + }; + + csi2_dphy4: csi2-dphy4 { + compatible = "rockchip,rk3588-csi2-dphy"; + rockchip,hw = <&csi2_dphy0_hw>, <&csi2_dphy1_hw>; + phys = <&mipidcphy0>, <&mipidcphy1>; + phy-names = "dcphy0", "dcphy1"; + status = "disabled"; + }; + + csi2_dphy5: csi2-dphy5 { + compatible = "rockchip,rk3588-csi2-dphy"; + rockchip,hw = <&csi2_dphy0_hw>, <&csi2_dphy1_hw>; + phys = <&mipidcphy0>, <&mipidcphy1>; + phy-names = "dcphy0", "dcphy1"; status = "disabled"; }; @@ -1860,6 +1892,58 @@ status = "disabled"; }; + /omit-if-no-ref/ + mipi_dcphy1: mipi_dcphy0: mipi-dcphy-dummy { + }; + + mipi0_csi2: mipi0-csi2 { + compatible = "rockchip,rk3588-mipi-csi2"; + rockchip,hw = <&mipi0_csi2_hw>, <&mipi1_csi2_hw>, + <&mipi2_csi2_hw>, <&mipi3_csi2_hw>, + <&mipi4_csi2_hw>, <&mipi5_csi2_hw>; + status = "disabled"; + }; + + mipi1_csi2: mipi1-csi2 { + compatible = "rockchip,rk3588-mipi-csi2"; + rockchip,hw = <&mipi0_csi2_hw>, <&mipi1_csi2_hw>, + <&mipi2_csi2_hw>, <&mipi3_csi2_hw>, + <&mipi4_csi2_hw>, <&mipi5_csi2_hw>; + status = "disabled"; + }; + + mipi2_csi2: mipi2-csi2 { + compatible = "rockchip,rk3588-mipi-csi2"; + rockchip,hw = <&mipi0_csi2_hw>, <&mipi1_csi2_hw>, + <&mipi2_csi2_hw>, <&mipi3_csi2_hw>, + <&mipi4_csi2_hw>, <&mipi5_csi2_hw>; + status = "disabled"; + }; + + mipi3_csi2: mipi3-csi2 { + compatible = "rockchip,rk3588-mipi-csi2"; + rockchip,hw = <&mipi0_csi2_hw>, <&mipi1_csi2_hw>, + <&mipi2_csi2_hw>, <&mipi3_csi2_hw>, + <&mipi4_csi2_hw>, <&mipi5_csi2_hw>; + status = "disabled"; + }; + + mipi4_csi2: mipi4-csi2 { + compatible = "rockchip,rk3588-mipi-csi2"; + rockchip,hw = <&mipi0_csi2_hw>, <&mipi1_csi2_hw>, + <&mipi2_csi2_hw>, <&mipi3_csi2_hw>, + <&mipi4_csi2_hw>, <&mipi5_csi2_hw>; + status = "disabled"; + }; + + mipi5_csi2: mipi5-csi2 { + compatible = "rockchip,rk3588-mipi-csi2"; + rockchip,hw = <&mipi0_csi2_hw>, <&mipi1_csi2_hw>, + <&mipi2_csi2_hw>, <&mipi3_csi2_hw>, + <&mipi4_csi2_hw>, <&mipi5_csi2_hw>; + status = "disabled"; + }; + mpp_srv: mpp-srv { compatible = "rockchip,mpp-service"; rockchip,taskqueue-count = <12>; @@ -4356,6 +4440,12 @@ power-domains = <&power RK3588_PD_VI>; rockchip,grf = <&sys_grf>; iommus = <&rkcif_mmu>; + nvmem-cells = <&specification_serial_number>, + <&package_serial_number_low>, + <&package_serial_number_high>; + nvmem-cell-names = "specification", + "package_low", + "package_high"; status = "disabled"; }; @@ -4373,8 +4463,8 @@ status = "disabled"; }; - mipi0_csi2: mipi0-csi2@fdd10000 { - compatible = "rockchip,rk3588-mipi-csi2"; + mipi0_csi2_hw: mipi0-csi2-hw@fdd10000 { + compatible = "rockchip,rk3588-mipi-csi2-hw"; reg = <0x0 0xfdd10000 0x0 0x10000>; reg-names = "csihost_regs"; interrupts = , @@ -4384,11 +4474,11 @@ clock-names = "pclk_csi2host"; resets = <&cru SRST_P_CSI_HOST_0>; reset-names = "srst_csihost_p"; - status = "disabled"; + status = "okay"; }; - mipi1_csi2: mipi1-csi2@fdd20000 { - compatible = "rockchip,rk3588-mipi-csi2"; + mipi1_csi2_hw: mipi1-csi2-hw@fdd20000 { + compatible = "rockchip,rk3588-mipi-csi2-hw"; reg = <0x0 0xfdd20000 0x0 0x10000>; reg-names = "csihost_regs"; interrupts = , @@ -4397,12 +4487,12 @@ clocks = <&cru PCLK_CSI_HOST_1>; clock-names = "pclk_csi2host"; resets = <&cru SRST_P_CSI_HOST_1>; - reset-names = "srst_csihost_p", "srst_csihost_vicap"; - status = "disabled"; + reset-names = "srst_csihost_p"; + status = "okay"; }; - mipi2_csi2: mipi2-csi2@fdd30000 { - compatible = "rockchip,rk3588-mipi-csi2"; + mipi2_csi2_hw: mipi2-csi2-hw@fdd30000 { + compatible = "rockchip,rk3588-mipi-csi2-hw"; reg = <0x0 0xfdd30000 0x0 0x10000>; reg-names = "csihost_regs"; interrupts = , @@ -4412,11 +4502,11 @@ clock-names = "pclk_csi2host"; resets = <&cru SRST_P_CSI_HOST_2>; reset-names = "srst_csihost_p"; - status = "disabled"; + status = "okay"; }; - mipi3_csi2: mipi3-csi2@fdd40000 { - compatible = "rockchip,rk3588-mipi-csi2"; + mipi3_csi2_hw: mipi3-csi2-hw@fdd40000 { + compatible = "rockchip,rk3588-mipi-csi2-hw"; reg = <0x0 0xfdd40000 0x0 0x10000>; reg-names = "csihost_regs"; interrupts = , @@ -4426,7 +4516,35 @@ clock-names = "pclk_csi2host"; resets = <&cru SRST_P_CSI_HOST_3>; reset-names = "srst_csihost_p"; - status = "disabled"; + status = "okay"; + }; + + mipi4_csi2_hw: mipi4-csi2-hw@fdd50000 { + compatible = "rockchip,rk3588-mipi-csi2-hw"; + reg = <0x0 0xfdd50000 0x0 0x10000>; + reg-names = "csihost_regs"; + interrupts = , + ; + interrupt-names = "csi-intr1", "csi-intr2"; + clocks = <&cru PCLK_CSI_HOST_4>; + clock-names = "pclk_csi2host"; + resets = <&cru SRST_P_CSI_HOST_4>; + reset-names = "srst_csihost_p"; + status = "okay"; + }; + + mipi5_csi2_hw: mipi5-csi2-hw@fdd60000 { + compatible = "rockchip,rk3588-mipi-csi2-hw"; + reg = <0x0 0xfdd60000 0x0 0x10000>; + reg-names = "csihost_regs"; + interrupts = , + ; + interrupt-names = "csi-intr1", "csi-intr2"; + clocks = <&cru PCLK_CSI_HOST_5>; + clock-names = "pclk_csi2host"; + resets = <&cru SRST_P_CSI_HOST_5>; + reset-names = "srst_csihost_p"; + status = "okay"; }; vop: vop@fdd90000 { @@ -4705,7 +4823,7 @@ resets = <&cru SRST_P_DSIHOST0>; reset-names = "apb"; power-domains = <&power RK3588_PD_VOP>; - phys = <&mipi_dcphy0>; + phys = <&mipidcphy0>; phy-names = "dcphy"; rockchip,grf = <&vop_grf>; #address-cells = <1>; @@ -4745,7 +4863,7 @@ resets = <&cru SRST_P_DSIHOST1>; reset-names = "apb"; power-domains = <&power RK3588_PD_VOP>; - phys = <&mipi_dcphy1>; + phys = <&mipidcphy1>; phy-names = "dcphy"; rockchip,grf = <&vop_grf>; #address-cells = <1>; @@ -6373,6 +6491,14 @@ cpu_code: cpu-code@2 { reg = <0x02 0x2>; }; + package_serial_number_high: package-serial-number-high@5 { + reg = <0x05 0x1>; + bits = <0 1>; + }; + package_serial_number_low: package-serial-number-low@6 { + reg = <0x06 0x1>; + bits = <5 3>; + }; specification_serial_number: specification-serial-number@6 { reg = <0x06 0x1>; bits = <0 5>; @@ -6521,7 +6647,7 @@ }; }; - mipi_dcphy0: phy@feda0000 { + mipidcphy0: phy@feda0000 { compatible = "rockchip,rk3588-mipi-dcphy"; reg = <0x0 0xfeda0000 0x0 0x10000>; rockchip,grf = <&mipidcphy0_grf>; @@ -6534,10 +6660,10 @@ <&cru SRST_S_MIPI_DCPHY0>; reset-names = "m_phy", "apb", "grf", "s_phy"; #phy-cells = <0>; - status = "disabled"; + status = "okay"; }; - mipi_dcphy1: phy@fedb0000 { + mipidcphy1: phy@fedb0000 { compatible = "rockchip,rk3588-mipi-dcphy"; reg = <0x0 0xfedb0000 0x0 0x10000>; rockchip,grf = <&mipidcphy1_grf>; @@ -6550,7 +6676,7 @@ <&cru SRST_S_MIPI_DCPHY1>; reset-names = "m_phy", "apb", "grf", "s_phy"; #phy-cells = <0>; - status = "disabled"; + status = "okay"; }; csi2_dphy0_hw: csi2-dphy0-hw@fedc0000 { @@ -6562,7 +6688,19 @@ reset-names = "srst_csiphy0", "srst_p_csiphy0"; rockchip,grf = <&mipidphy0_grf>; rockchip,sys_grf = <&sys_grf>; - status = "disabled"; + status = "okay"; + }; + + csi2_dphy1_hw: csi2-dphy1-hw@fedc8000 { + compatible = "rockchip,rk3588-csi2-dphy-hw"; + reg = <0x0 0xfedc8000 0x0 0x8000>; + clocks = <&cru PCLK_CSIPHY1>; + clock-names = "pclk"; + resets = <&cru SRST_CSIPHY1>, <&cru SRST_P_CSIPHY1>; + reset-names = "srst_csiphy1", "srst_p_csiphy1"; + rockchip,grf = <&mipidphy1_grf>; + rockchip,sys_grf = <&sys_grf>; + status = "okay"; }; combphy0_ps: phy@fee00000 { diff --git a/arch/arm64/configs/rk3308bs_mipi_display.config b/arch/arm64/configs/rk3308bs_mipi_display.config new file mode 100644 index 000000000000..24498f0aed59 --- /dev/null +++ b/arch/arm64/configs/rk3308bs_mipi_display.config @@ -0,0 +1,128 @@ +CONFIG_CMA=y +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_MFD_RK618=y +CONFIG_CLK_RK618=y +CONFIG_CMA_ALIGNMENT=8 +CONFIG_CMA_AREAS=7 +# CONFIG_CMA_DEBUG is not set +# CONFIG_CMA_DEBUGFS is not set +# CONFIG_CMA_INACTIVE is not set +CONFIG_CMA_SIZE_MBYTES=16 +# CONFIG_CMA_SIZE_SEL_MAX is not set +CONFIG_CMA_SIZE_SEL_MBYTES=y +# CONFIG_CMA_SIZE_SEL_MIN is not set +# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set +# CONFIG_CMA_SYSFS is not set +CONFIG_COMMON_CLK_ROCKCHIP_REGMAP=y +CONFIG_CONTIG_ALLOC=y +CONFIG_DMA_CMA=y +# CONFIG_DMA_PERNUMA_CMA is not set +CONFIG_DRM_MIPI_DSI=y +# CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_NT35596 is not set +# CONFIG_DRM_PANEL_BOE_HIMAX8279D is not set +# CONFIG_DRM_PANEL_BOE_TV101WUM_NL6 is not set +# CONFIG_DRM_PANEL_ELIDA_KD35T133 is not set +# CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02 is not set +# CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D is not set +# CONFIG_DRM_PANEL_ILITEK_ILI9881C is not set +# CONFIG_DRM_PANEL_INNOLUX_P079ZCA is not set +# CONFIG_DRM_PANEL_JDI_LT070ME05000 is not set +# CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04 is not set +# CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W is not set +# CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829 is not set +# CONFIG_DRM_PANEL_MANTIX_MLAF057WE51 is not set +# CONFIG_DRM_PANEL_NOVATEK_NT35510 is not set +# CONFIG_DRM_PANEL_ORISETECH_OTM8009A is not set +# CONFIG_DRM_PANEL_OSD_OSD101T2587_53TS is not set +# CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00 is not set +# CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN is not set +# CONFIG_DRM_PANEL_RAYDIUM_RM67191 is not set +# CONFIG_DRM_PANEL_RAYDIUM_RM68200 is not set +# CONFIG_DRM_PANEL_RONBO_RB070D30 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6D16D0 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03 is not set +# CONFIG_DRM_PANEL_SHARP_LQ101R1SX01 is not set +# CONFIG_DRM_PANEL_SHARP_LS043T1LE01 is not set +# CONFIG_DRM_PANEL_SITRONIX_ST7701 is not set +# CONFIG_DRM_PANEL_SITRONIX_ST7703 is not set +# CONFIG_DRM_PANEL_SONY_ACX424AKP is not set +# CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA is not set +# CONFIG_DRM_PANEL_VISIONOX_RM69299 is not set +# CONFIG_DRM_PANEL_XINPENG_XPP055C272 is not set +CONFIG_DRM_ROCKCHIP_RK618=y +CONFIG_MEMORY_ISOLATION=y +# CONFIG_RK628_MISC is not set +# CONFIG_RK_CMA_PROCFS is not set +# CONFIG_SND_SOC_ROCKCHIP_I2S_TDM_MULTI_LANES is not set +# CONFIG_TOUCHSCREEN_AD7877 is not set +# CONFIG_TOUCHSCREEN_AD7879 is not set +# CONFIG_TOUCHSCREEN_ADC is not set +# CONFIG_TOUCHSCREEN_ADS7846 is not set +# CONFIG_TOUCHSCREEN_AR1021_I2C is not set +# CONFIG_TOUCHSCREEN_ATMEL_MXT is not set +# CONFIG_TOUCHSCREEN_AUO_PIXCIR is not set +# CONFIG_TOUCHSCREEN_BU21013 is not set +# CONFIG_TOUCHSCREEN_BU21029 is not set +# CONFIG_TOUCHSCREEN_CHIPONE_ICN8318 is not set +# CONFIG_TOUCHSCREEN_CY8CTMA140 is not set +# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set +# CONFIG_TOUCHSCREEN_CYTTSP4_CORE is not set +# CONFIG_TOUCHSCREEN_CYTTSP_CORE is not set +# CONFIG_TOUCHSCREEN_DYNAPRO is not set +# CONFIG_TOUCHSCREEN_EDT_FT5X06 is not set +# CONFIG_TOUCHSCREEN_EETI is not set +# CONFIG_TOUCHSCREEN_EGALAX is not set +# CONFIG_TOUCHSCREEN_EGALAX_SERIAL is not set +# CONFIG_TOUCHSCREEN_EKTF2127 is not set +# CONFIG_TOUCHSCREEN_ELAN is not set +# CONFIG_TOUCHSCREEN_ELAN5515 is not set +# CONFIG_TOUCHSCREEN_ELO is not set +# CONFIG_TOUCHSCREEN_EXC3000 is not set +# CONFIG_TOUCHSCREEN_FTS is not set +# CONFIG_TOUCHSCREEN_FUJITSU is not set +# CONFIG_TOUCHSCREEN_GOODIX is not set +# CONFIG_TOUCHSCREEN_GSL3673 is not set +# CONFIG_TOUCHSCREEN_GSL3673_800X1280 is not set +# CONFIG_TOUCHSCREEN_GSLX680_PAD is not set +CONFIG_TOUCHSCREEN_GT1X=y +# CONFIG_TOUCHSCREEN_GUNZE is not set +# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set +# CONFIG_TOUCHSCREEN_HIDEEP is not set +# CONFIG_TOUCHSCREEN_ILI210X is not set +# CONFIG_TOUCHSCREEN_IMX6UL_TSC is not set +# CONFIG_TOUCHSCREEN_INEXIO is not set +# CONFIG_TOUCHSCREEN_IQS5XX is not set +# CONFIG_TOUCHSCREEN_MAX11801 is not set +# CONFIG_TOUCHSCREEN_MCS5000 is not set +# CONFIG_TOUCHSCREEN_MELFAS_MIP4 is not set +# CONFIG_TOUCHSCREEN_MK712 is not set +# CONFIG_TOUCHSCREEN_MMS114 is not set +# CONFIG_TOUCHSCREEN_MTOUCH is not set +# CONFIG_TOUCHSCREEN_PENMOUNT is not set +# CONFIG_TOUCHSCREEN_PIXCIR is not set +CONFIG_TOUCHSCREEN_PROPERTIES=y +# CONFIG_TOUCHSCREEN_RM_TS is not set +# CONFIG_TOUCHSCREEN_ROHM_BU21023 is not set +# CONFIG_TOUCHSCREEN_S6SY761 is not set +# CONFIG_TOUCHSCREEN_SILEAD is not set +# CONFIG_TOUCHSCREEN_SIS_I2C is not set +# CONFIG_TOUCHSCREEN_ST1232 is not set +# CONFIG_TOUCHSCREEN_STMFTS is not set +# CONFIG_TOUCHSCREEN_SURFACE3_SPI is not set +# CONFIG_TOUCHSCREEN_SX8654 is not set +# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set +# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set +# CONFIG_TOUCHSCREEN_TOUCHWIN is not set +# CONFIG_TOUCHSCREEN_TPS6507X is not set +# CONFIG_TOUCHSCREEN_TSC2004 is not set +# CONFIG_TOUCHSCREEN_TSC2005 is not set +# CONFIG_TOUCHSCREEN_TSC2007 is not set +# CONFIG_TOUCHSCREEN_TSC_SERIO is not set +# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set +# CONFIG_TOUCHSCREEN_WACOM_I2C is not set +# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set +# CONFIG_TOUCHSCREEN_WDT87XX_I2C is not set +# CONFIG_TOUCHSCREEN_ZET6223 is not set +# CONFIG_TOUCHSCREEN_ZFORCE is not set +# CONFIG_TOUCHSCREEN_ZINITIX is not set diff --git a/arch/arm64/configs/rockchip_defconfig b/arch/arm64/configs/rockchip_defconfig index 779b915c2719..ed2421e2ce76 100644 --- a/arch/arm64/configs/rockchip_defconfig +++ b/arch/arm64/configs/rockchip_defconfig @@ -635,6 +635,7 @@ CONFIG_DRM_ROCKCHIP_RK618=y CONFIG_DRM_ROCKCHIP_RK628=y CONFIG_DRM_PANEL_SIMPLE=y CONFIG_DRM_PANEL_MAXIM_MAX96752F=y +CONFIG_DRM_PANEL_MAXIM_MAX96772=y CONFIG_DRM_DISPLAY_CONNECTOR=y CONFIG_DRM_MAXIM_MAX96745=y CONFIG_DRM_MAXIM_MAX96755F=y @@ -715,6 +716,7 @@ CONFIG_SND_SOC_RK817=y CONFIG_SND_SOC_RK_CODEC_DIGITAL=y CONFIG_SND_SOC_RK_DSM=y CONFIG_SND_SOC_RT5640=y +CONFIG_SND_SOC_RT5651=y CONFIG_SND_SOC_SPDIF=y CONFIG_SND_SOC_AW883XX=y CONFIG_SND_SIMPLE_CARD=y diff --git a/drivers/cpufreq/rockchip-cpufreq.c b/drivers/cpufreq/rockchip-cpufreq.c index ce3e08a22b55..804fcfd1ed1c 100644 --- a/drivers/cpufreq/rockchip-cpufreq.c +++ b/drivers/cpufreq/rockchip-cpufreq.c @@ -605,11 +605,13 @@ static int rockchip_cpufreq_cluster_init(int cpu, struct cluster_info *cluster) } if (opp_info->data && opp_info->data->get_soc_info) opp_info->data->get_soc_info(dev, np, &bin, &process); + rockchip_get_soc_info(dev, np, &bin, &process); rockchip_get_scale_volt_sel(dev, "cpu_leakage", reg_name, bin, process, &cluster->scale, &volt_sel); if (opp_info->data && opp_info->data->set_soc_info) opp_info->data->set_soc_info(dev, np, bin, process, volt_sel); pname_table = rockchip_set_opp_prop_name(dev, process, volt_sel); + rockchip_set_opp_supported_hw(dev, np, bin, volt_sel); if (of_find_property(dev->of_node, "cpu-supply", NULL) && of_find_property(dev->of_node, "mem-supply", NULL)) { diff --git a/drivers/crypto/rockchip/rk_crypto_core.c b/drivers/crypto/rockchip/rk_crypto_core.c index 56a50d5c01de..2a9cf2da6372 100644 --- a/drivers/crypto/rockchip/rk_crypto_core.c +++ b/drivers/crypto/rockchip/rk_crypto_core.c @@ -272,9 +272,17 @@ static void start_irq_timer(struct rk_crypto_dev *rk_dev) static void rk_crypto_irq_timer_handle(struct timer_list *t) { struct rk_crypto_dev *rk_dev = from_timer(rk_dev, t, timer); + unsigned long flags; + + spin_lock_irqsave(&rk_dev->lock, flags); rk_dev->err = -ETIMEDOUT; rk_dev->stat.timeout_cnt++; + + rk_unload_data(rk_dev); + + spin_unlock_irqrestore(&rk_dev->lock, flags); + tasklet_schedule(&rk_dev->done_task); } @@ -282,8 +290,12 @@ static irqreturn_t rk_crypto_irq_handle(int irq, void *dev_id) { struct rk_crypto_dev *rk_dev = platform_get_drvdata(dev_id); struct rk_alg_ctx *alg_ctx; + unsigned long flags; - spin_lock(&rk_dev->lock); + spin_lock_irqsave(&rk_dev->lock, flags); + + /* reset timeout timer */ + start_irq_timer(rk_dev); alg_ctx = rk_alg_ctx_cast(rk_dev->async_req); @@ -292,9 +304,14 @@ static irqreturn_t rk_crypto_irq_handle(int irq, void *dev_id) if (alg_ctx->ops.irq_handle) alg_ctx->ops.irq_handle(irq, dev_id); - tasklet_schedule(&rk_dev->done_task); + /* already trigger timeout */ + if (rk_dev->err != -ETIMEDOUT) { + spin_unlock_irqrestore(&rk_dev->lock, flags); + tasklet_schedule(&rk_dev->done_task); + } else { + spin_unlock_irqrestore(&rk_dev->lock, flags); + } - spin_unlock(&rk_dev->lock); return IRQ_HANDLED; } diff --git a/drivers/crypto/rockchip/rk_crypto_utils.c b/drivers/crypto/rockchip/rk_crypto_utils.c index 5db73ab1628c..5758e0eede97 100644 --- a/drivers/crypto/rockchip/rk_crypto_utils.c +++ b/drivers/crypto/rockchip/rk_crypto_utils.c @@ -72,14 +72,18 @@ static int check_scatter_align(struct scatterlist *sg_src, { int in, out, align; + /* The last piece has no need for length alignment */ in = IS_ALIGNED((u32)sg_src->offset, 4) && - IS_ALIGNED((u32)sg_src->length, align_mask) && + (!sg_next(sg_src) || + IS_ALIGNED((u32)sg_src->length, align_mask)) && (sg_phys(sg_src) < SZ_4G); if (!sg_dst) return in; + /* The last piece has no need for length alignment */ out = IS_ALIGNED((u32)sg_dst->offset, 4) && - IS_ALIGNED((u32)sg_dst->length, align_mask) && + (!sg_next(sg_dst) || + IS_ALIGNED((u32)sg_dst->length, align_mask)) && (sg_phys(sg_dst) < SZ_4G); align = in && out; diff --git a/drivers/crypto/rockchip/rk_crypto_v2_ahash.c b/drivers/crypto/rockchip/rk_crypto_v2_ahash.c index dd9ea240bac0..919603ff4768 100644 --- a/drivers/crypto/rockchip/rk_crypto_v2_ahash.c +++ b/drivers/crypto/rockchip/rk_crypto_v2_ahash.c @@ -58,6 +58,10 @@ static void rk_hash_reset(struct rk_crypto_dev *rk_dev) pool_timeout_us); CRYPTO_WRITE(rk_dev, CRYPTO_HASH_CTL, 0xffff0000); + + /* clear dma int status */ + tmp = CRYPTO_READ(rk_dev, CRYPTO_DMA_INT_ST); + CRYPTO_WRITE(rk_dev, CRYPTO_DMA_INT_ST, tmp); } static int rk_crypto_irq_handle(int irq, void *dev_id) diff --git a/drivers/crypto/rockchip/rk_crypto_v2_skcipher.c b/drivers/crypto/rockchip/rk_crypto_v2_skcipher.c index 2a4628f9f58a..2bfff0d28771 100644 --- a/drivers/crypto/rockchip/rk_crypto_v2_skcipher.c +++ b/drivers/crypto/rockchip/rk_crypto_v2_skcipher.c @@ -197,6 +197,10 @@ static void rk_cipher_reset(struct rk_crypto_dev *rk_dev) pool_timeout_us); CRYPTO_WRITE(rk_dev, CRYPTO_BC_CTL, 0xffff0000); + + /* clear dma int status */ + tmp = CRYPTO_READ(rk_dev, CRYPTO_DMA_INT_ST); + CRYPTO_WRITE(rk_dev, CRYPTO_DMA_INT_ST, tmp); } static void rk_crypto_complete(struct crypto_async_request *base, int err) diff --git a/drivers/crypto/rockchip/rk_crypto_v3_ahash.c b/drivers/crypto/rockchip/rk_crypto_v3_ahash.c index f39026dbc314..0c91b45b2123 100644 --- a/drivers/crypto/rockchip/rk_crypto_v3_ahash.c +++ b/drivers/crypto/rockchip/rk_crypto_v3_ahash.c @@ -63,6 +63,10 @@ static void rk_hash_reset(struct rk_crypto_dev *rk_dev) pool_timeout_us); CRYPTO_WRITE(rk_dev, CRYPTO_HASH_CTL, 0xffff0000); + + /* clear dma int status */ + tmp = CRYPTO_READ(rk_dev, CRYPTO_DMA_INT_ST); + CRYPTO_WRITE(rk_dev, CRYPTO_DMA_INT_ST, tmp); } static int rk_hash_mid_data_store(struct rk_crypto_dev *rk_dev, struct rk_hash_mid_data *mid_data) diff --git a/drivers/crypto/rockchip/rk_crypto_v3_skcipher.c b/drivers/crypto/rockchip/rk_crypto_v3_skcipher.c index 26d2b714761c..4220e6cbeb14 100644 --- a/drivers/crypto/rockchip/rk_crypto_v3_skcipher.c +++ b/drivers/crypto/rockchip/rk_crypto_v3_skcipher.c @@ -196,6 +196,10 @@ static void rk_cipher_reset(struct rk_crypto_dev *rk_dev) pool_timeout_us); CRYPTO_WRITE(rk_dev, CRYPTO_BC_CTL, 0xffff0000); + + /* clear dma int status */ + tmp = CRYPTO_READ(rk_dev, CRYPTO_DMA_INT_ST); + CRYPTO_WRITE(rk_dev, CRYPTO_DMA_INT_ST, tmp); } static void rk_crypto_complete(struct crypto_async_request *base, int err) diff --git a/drivers/gpu/drm/bridge/maxim-max96755f.c b/drivers/gpu/drm/bridge/maxim-max96755f.c index bfabb61c166a..95dcd52c0900 100644 --- a/drivers/gpu/drm/bridge/maxim-max96755f.c +++ b/drivers/gpu/drm/bridge/maxim-max96755f.c @@ -41,6 +41,7 @@ struct max96755f_bridge { bool dv_swp_ab; bool dpi_deskew_en; bool split_mode; + bool bridge_dual_link; u32 dsi_lane_map[4]; struct { @@ -283,7 +284,7 @@ static void max96755f_bridge_pre_enable(struct drm_bridge *bridge) static void max96755f_bridge_reset_oneshot(struct max96755f_bridge *ser) { - regmap_update_bits(ser->regmap, 0x10, RESET_ONESHOT, + regmap_update_bits(ser->regmap, 0x0010, RESET_ONESHOT, FIELD_PREP(RESET_ONESHOT, 1)); mdelay(100); @@ -324,6 +325,12 @@ static void max96755f_bridge_enable(struct drm_bridge *bridge) FIELD_PREP(START_PORTAY, 1)); regmap_update_bits(ser->regmap, 0x02, VID_TX_EN_X, FIELD_PREP(VID_TX_EN_X, 1)); + if (ser->bridge_dual_link) { + regmap_update_bits(ser->regmap, 0x0010, + AUTO_LINK | LINK_CFG, + FIELD_PREP(AUTO_LINK, 0) | + FIELD_PREP(LINK_CFG, DUAL_LINK)); + } } max96755f_bridge_reset_oneshot(ser); @@ -358,7 +365,7 @@ static void max96755f_bridge_disable(struct drm_bridge *bridge) FIELD_PREP(VID_TX_EN_X, 0) | FIELD_PREP(VID_TX_EN_Y, 0)); - if (ser->split_mode) + if (ser->split_mode || ser->bridge_dual_link) regmap_update_bits(ser->regmap, 0x0010, AUTO_LINK | LINK_CFG, FIELD_PREP(AUTO_LINK, 1) | @@ -487,6 +494,7 @@ static irqreturn_t max96755f_bridge_lock_irq_handler(int irq, void *arg) static int max96755f_bridge_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; struct max96755f_bridge *ser; int ret; @@ -529,6 +537,8 @@ static int max96755f_bridge_probe(struct platform_device *pdev) if (ret) return dev_err_probe(dev, ret, "failed to request lock IRQ\n"); + ser->bridge_dual_link = of_property_read_bool(np, "bridge_dual_link"); + ser->bridge.funcs = &max96755f_bridge_funcs; ser->bridge.of_node = dev->of_node; ser->bridge.ops = DRM_BRIDGE_OP_DETECT; diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c index 7ea4a5468986..2f23b7d71163 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c @@ -221,6 +221,7 @@ struct dw_hdmi_phy_data { struct dw_hdmi_qp { struct drm_connector connector; struct drm_bridge bridge; + struct drm_bridge *next_bridge; struct drm_panel *panel; struct platform_device *hdcp_dev; struct platform_device *audio; @@ -256,6 +257,7 @@ struct dw_hdmi_qp { bool cec_enable; bool allm_enable; bool support_hdmi; + bool skip_connector; int force_output; int vp_id; int old_vp_id; @@ -2057,6 +2059,9 @@ dw_hdmi_connector_detect(struct drm_connector *connector, bool force) if (hdmi->panel) return connector_status_connected; + if (hdmi->next_bridge && hdmi->next_bridge->ops & DRM_BRIDGE_OP_DETECT) + return drm_bridge_detect(hdmi->next_bridge); + if (hdmi->plat_data->left) secondary = hdmi->plat_data->left; else if (hdmi->plat_data->right) @@ -2136,9 +2141,21 @@ static int dw_hdmi_connector_get_modes(struct drm_connector *connector) void *data = hdmi->plat_data->phy_data; int i, ret = 0; + if (hdmi->plat_data->right && hdmi->plat_data->right->next_bridge) { + struct drm_bridge *bridge = hdmi->plat_data->right->next_bridge; + + if (bridge->ops & DRM_BRIDGE_OP_MODES) { + if (!drm_bridge_get_modes(bridge, connector)) + return 0; + } + } + if (hdmi->panel) return drm_panel_get_modes(hdmi->panel, connector); + if (hdmi->next_bridge && hdmi->next_bridge->ops & DRM_BRIDGE_OP_MODES) + return drm_bridge_get_modes(hdmi->next_bridge, connector); + if (!hdmi->ddc) return 0; @@ -2682,13 +2699,31 @@ static int dw_hdmi_qp_bridge_attach(struct drm_bridge *bridge, struct drm_connector *connector = &hdmi->connector; struct cec_connector_info conn_info; struct cec_notifier *notifier; + bool skip_connector = false; - if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR) + if (hdmi->next_bridge) { + struct drm_bridge *next_bridge = hdmi->next_bridge; + int ret; + + ret = drm_bridge_attach(bridge->encoder, next_bridge, bridge, + next_bridge->ops & DRM_BRIDGE_OP_MODES ? + DRM_BRIDGE_ATTACH_NO_CONNECTOR : 0); + if (ret) { + DRM_ERROR("failed to attach next bridge: %d\n", ret); + return ret; + } + + skip_connector = !(next_bridge->ops & DRM_BRIDGE_OP_MODES); + } + + hdmi->skip_connector = skip_connector; + if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR || skip_connector) return 0; connector->interlace_allowed = 1; connector->polled = DRM_CONNECTOR_POLL_HPD; - + if (hdmi->next_bridge && hdmi->next_bridge->ops & DRM_BRIDGE_OP_DETECT) + connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT; drm_connector_helper_add(connector, &dw_hdmi_connector_helper_funcs); drm_connector_init(bridge->dev, connector, &dw_hdmi_connector_funcs, @@ -3352,10 +3387,11 @@ __dw_hdmi_probe(struct platform_device *pdev, struct dw_hdmi_qp_cec_data cec; struct resource *iores = NULL; struct drm_panel *panel = NULL; + struct drm_bridge *bridge = NULL; int irq; int ret; - ret = drm_of_find_panel_or_bridge(np, 1, -1, &panel, NULL); + ret = drm_of_find_panel_or_bridge(np, 1, -1, &panel, &bridge); if (ret < 0 && ret != -ENODEV) return ERR_PTR(ret); @@ -3364,6 +3400,7 @@ __dw_hdmi_probe(struct platform_device *pdev, return ERR_PTR(-ENOMEM); hdmi->panel = panel; + hdmi->next_bridge = bridge; hdmi->connector.stereo_allowed = 1; hdmi->plat_data = plat_data; hdmi->dev = dev; @@ -3646,6 +3683,10 @@ struct dw_hdmi_qp *dw_hdmi_qp_bind(struct platform_device *pdev, } plat_data->connector = &hdmi->connector; + if (hdmi->skip_connector && hdmi->next_bridge) + plat_data->bridge = hdmi->next_bridge; + else + plat_data->bridge = NULL; } if (plat_data->split_mode && !hdmi->plat_data->first_screen) { diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c index 1d137af13e73..3a33cb5889b7 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c @@ -876,20 +876,28 @@ static void dw_mipi_dsi_post_disable(struct dw_mipi_dsi *dsi) static void dw_mipi_dsi_bridge_post_disable(struct drm_bridge *bridge) { struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge); + const struct dw_mipi_dsi_plat_data *pdata = dsi->plat_data; if (dsi->panel) drm_panel_unprepare(dsi->panel); dw_mipi_dsi_post_disable(dsi); + + if (pdata->stream_standby) + pdata->stream_standby(pdata->priv_data, 0); } static void dw_mipi_dsi_bridge_disable(struct drm_bridge *bridge) { struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge); + const struct dw_mipi_dsi_plat_data *pdata = dsi->plat_data; if (dsi->panel) drm_panel_disable(dsi->panel); + if (pdata->stream_standby) + pdata->stream_standby(pdata->priv_data, 1); + dw_mipi_dsi_disable(dsi); } @@ -975,6 +983,10 @@ static void dw_mipi_dsi_pre_enable(struct dw_mipi_dsi *dsi) static void dw_mipi_dsi_bridge_pre_enable(struct drm_bridge *bridge) { struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge); + const struct dw_mipi_dsi_plat_data *pdata = dsi->plat_data; + + if (pdata->stream_standby) + pdata->stream_standby(pdata->priv_data, 1); dw_mipi_dsi_pre_enable(dsi); @@ -1006,9 +1018,13 @@ static void dw_mipi_dsi_enable(struct dw_mipi_dsi *dsi) static void dw_mipi_dsi_bridge_enable(struct drm_bridge *bridge) { struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge); + const struct dw_mipi_dsi_plat_data *pdata = dsi->plat_data; dw_mipi_dsi_enable(dsi); + if (pdata->stream_standby) + pdata->stream_standby(pdata->priv_data, 0); + if (dsi->panel) drm_panel_enable(dsi->panel); diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig index 2794dd34726f..c04e091233f1 100644 --- a/drivers/gpu/drm/panel/Kconfig +++ b/drivers/gpu/drm/panel/Kconfig @@ -236,6 +236,14 @@ config DRM_PANEL_MAXIM_MAX96752F Say Y if you want to enable support for panels based on the Maxim MAX96752F. +config DRM_PANEL_MAXIM_MAX96772 + tristate "Maxim MAX96772-based panels" + depends on OF + depends on BACKLIGHT_CLASS_DEVICE + help + Say Y if you want to enable support for panels based on the + Maxim MAX96772. + config DRM_PANEL_OLIMEX_LCD_OLINUXINO tristate "Olimex LCD-OLinuXino panel" depends on OF diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile index d99b1eaf92c2..f28d98218387 100644 --- a/drivers/gpu/drm/panel/Makefile +++ b/drivers/gpu/drm/panel/Makefile @@ -22,6 +22,7 @@ obj-$(CONFIG_DRM_PANEL_NOVATEK_NT35510) += panel-novatek-nt35510.o obj-$(CONFIG_DRM_PANEL_NOVATEK_NT39016) += panel-novatek-nt39016.o obj-$(CONFIG_DRM_PANEL_MANTIX_MLAF057WE51) += panel-mantix-mlaf057we51.o obj-$(CONFIG_DRM_PANEL_MAXIM_MAX96752F) += panel-maxim-max96752f.o +obj-$(CONFIG_DRM_PANEL_MAXIM_MAX96772) += panel-maxim-max96772.o obj-$(CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO) += panel-olimex-lcd-olinuxino.o obj-$(CONFIG_DRM_PANEL_ORISETECH_OTM8009A) += panel-orisetech-otm8009a.o obj-$(CONFIG_DRM_PANEL_OSD_OSD101T2587_53TS) += panel-osd-osd101t2587-53ts.o diff --git a/drivers/gpu/drm/panel/panel-maxim-max96772.c b/drivers/gpu/drm/panel/panel-maxim-max96772.c new file mode 100644 index 000000000000..2e16d0337887 --- /dev/null +++ b/drivers/gpu/drm/panel/panel-maxim-max96772.c @@ -0,0 +1,543 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2022 Rockchip Electronics Co. Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include