diff --git a/arch/arm64/boot/dts/rockchip/rk3566.dtsi b/arch/arm64/boot/dts/rockchip/rk3566.dtsi
index 4ac532cd1ca4..3a9f6cdf4b7e 100644
--- a/arch/arm64/boot/dts/rockchip/rk3566.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3566.dtsi
@@ -15,6 +15,27 @@
 	/delete-node/ opp-1992000000;
 };
 
+&dmc {
+	system-status-freq = <
+		/*system status         freq(KHz)*/
+		SYS_STATUS_NORMAL       780000
+		SYS_STATUS_REBOOT       1056000
+		SYS_STATUS_SUSPEND      324000
+		SYS_STATUS_VIDEO_1080P  528000
+		SYS_STATUS_BOOST        1056000
+		SYS_STATUS_ISP          1056000
+		SYS_STATUS_PERFORMANCE  1056000
+	>;
+};
+
+&dmc_opp_table {
+	opp-1056000000 {
+		opp-hz = /bits/ 64 <1056000000>;
+		opp-microvolt = <900000>;
+	};
+	/delete-node/ opp-1560000000;
+};
+
 &power {
 	pd_pipe@RK3568_PD_PIPE {
 		reg = <RK3568_PD_PIPE>;
diff --git a/arch/arm64/boot/dts/rockchip/rk3568-dram-default-timing.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-dram-default-timing.dtsi
new file mode 100644
index 000000000000..43f978809c02
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3568-dram-default-timing.dtsi
@@ -0,0 +1,81 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
+ */
+
+#include <dt-bindings/clock/rockchip-ddr.h>
+#include <dt-bindings/memory/rk3568-dram.h>
+
+/ {
+	ddr_timing: ddr_timing {
+		compatible = "rockchip,ddr-timing";
+		ddr2_speed_bin = <DDR2_DEFAULT>;
+		ddr3_speed_bin = <DDR3_DEFAULT>;
+		ddr4_speed_bin = <DDR4_DEFAULT>;
+		pd_idle = <13>;
+		sr_idle = <93>;
+		sr_mc_gate_idle = <0>;
+		srpd_lite_idle = <0>;
+		standby_idle = <0>;
+
+		auto_pd_dis_freq = <1066>;
+		auto_sr_dis_freq = <800>;
+		ddr2_dll_dis_freq = <300>;
+		ddr3_dll_dis_freq = <300>;
+		ddr4_dll_dis_freq = <625>;
+		phy_dll_dis_freq = <400>;
+
+		ddr2_odt_dis_freq = <100>;
+		phy_ddr2_odt_dis_freq = <100>;
+		ddr2_drv = <DDR2_DS_REDUCE>;
+		ddr2_odt = <DDR2_ODT_150ohm>;
+		phy_ddr2_ca_drv = <PHY_DDR4_DS_ODT_DISABLE>;
+		phy_ddr2_ck_drv = <PHY_DDR4_DS_ODT_DISABLE>;
+		phy_ddr2_dq_drv = <PHY_DDR4_DS_ODT_DISABLE>;
+		phy_ddr2_odt = <PHY_DDR4_DS_ODT_DISABLE>;
+
+		ddr3_odt_dis_freq = <333>;
+		phy_ddr3_odt_dis_freq = <333>;
+		ddr3_drv = <DDR3_DS_34ohm>;
+		ddr3_odt = <DDR3_ODT_120ohm>;
+		phy_ddr3_ca_drv = <PHY_DDR4_DS_ODT_DISABLE>;
+		phy_ddr3_ck_drv = <PHY_DDR4_DS_ODT_DISABLE>;
+		phy_ddr3_dq_drv = <PHY_DDR4_DS_ODT_DISABLE>;
+		phy_ddr3_odt = <PHY_DDR4_DS_ODT_DISABLE>;
+
+		phy_lpddr2_odt_dis_freq = <333>;
+		lpddr2_drv = <LP2_DS_40ohm>;
+		phy_lpddr2_ca_drv = <PHY_DDR4_DS_ODT_DISABLE>;
+		phy_lpddr2_ck_drv = <PHY_DDR4_DS_ODT_DISABLE>;
+		phy_lpddr2_dq_drv = <PHY_DDR4_DS_ODT_DISABLE>;
+		phy_lpddr2_odt = <PHY_DDR4_DS_ODT_DISABLE>;
+
+		lpddr3_odt_dis_freq = <333>;
+		phy_lpddr3_odt_dis_freq = <333>;
+		lpddr3_drv = <LP3_DS_34ohm>;
+		lpddr3_odt = <LP3_ODT_120ohm>;
+		phy_lpddr3_ca_drv = <PHY_DDR4_DS_ODT_DISABLE>;
+		phy_lpddr3_ck_drv = <PHY_DDR4_DS_ODT_DISABLE>;
+		phy_lpddr3_dq_drv = <PHY_DDR4_DS_ODT_DISABLE>;
+		phy_lpddr3_odt = <PHY_DDR4_DS_ODT_DISABLE>;
+
+		lpddr4_odt_dis_freq = <333>;
+		phy_lpddr4_odt_dis_freq = <333>;
+		lpddr4_drv = <LP4_PDDS_40ohm>;
+		lpddr4_dq_odt = <LP4_DQ_ODT_240ohm>;
+		lpddr4_ca_odt = <LP4_CA_ODT_DIS>;
+		phy_lpddr4_ca_drv = <PHY_DDR4_DS_ODT_DISABLE>;
+		phy_lpddr4_ck_cs_drv = <PHY_DDR4_DS_ODT_DISABLE>;
+		phy_lpddr4_dq_drv = <PHY_DDR4_DS_ODT_DISABLE>;
+		phy_lpddr4_odt = <PHY_DDR4_DS_ODT_DISABLE>;
+
+		ddr4_odt_dis_freq = <625>;
+		phy_ddr4_odt_dis_freq = <625>;
+		ddr4_drv = <DDR4_DS_34ohm>;
+		ddr4_odt = <DDR4_ODT_120ohm>;
+		phy_ddr4_ca_drv = <PHY_DDR4_DS_ODT_DISABLE>;
+		phy_ddr4_ck_drv = <PHY_DDR4_DS_ODT_DISABLE>;
+		phy_ddr4_dq_drv = <PHY_DDR4_DS_ODT_DISABLE>;
+		phy_ddr4_odt = <PHY_DDR4_DS_ODT_DISABLE>;
+	};
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
index e00bad98f152..deb45b2abeba 100644
--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
@@ -10,6 +10,8 @@
 #include <dt-bindings/soc/rockchip,boot-mode.h>
 #include <dt-bindings/phy/phy.h>
 #include <dt-bindings/power/rk3568-power.h>
+#include <dt-bindings/soc/rockchip-system-status.h>
+#include "rk3568-dram-default-timing.dtsi"
 
 / {
 	compatible = "rockchip,rk3568";
@@ -1734,6 +1736,66 @@
 		status = "disabled";
 	};
 
+	dfi: dfi@fe230000 {
+		reg = <0x00 0xfe230000 0x00 0x400>;
+		compatible = "rockchip,rk3568-dfi";
+		rockchip,pmugrf = <&pmugrf>;
+		status = "disabled";
+	};
+
+	dmc: dmc {
+		compatible = "rockchip,rk3568-dmc";
+		interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "complete";
+		devfreq-events = <&dfi>;
+		clocks = <&cru SCLK_DDRCLK>;
+		clock-names = "dmc_clk";
+		operating-points-v2 = <&dmc_opp_table>;
+		ddr_timing = <&ddr_timing>;
+		upthreshold = <40>;
+		downdifferential = <20>;
+		system-status-freq = <
+			/*system status         freq(KHz)*/
+			SYS_STATUS_NORMAL       780000
+			SYS_STATUS_REBOOT       1560000
+			SYS_STATUS_SUSPEND      324000
+			SYS_STATUS_VIDEO_1080P  528000
+			SYS_STATUS_BOOST        1560000
+			SYS_STATUS_ISP          1560000
+			SYS_STATUS_PERFORMANCE  1560000
+		>;
+		auto-min-freq = <324000>;
+		auto-freq-en = <1>;
+		#cooling-cells = <2>;
+		status = "disabled";
+	};
+
+	dmc_opp_table: dmc-opp-table {
+		compatible = "operating-points-v2";
+
+		opp-324000000 {
+			opp-hz = /bits/ 64 <324000000>;
+			opp-microvolt = <900000>;
+		};
+		opp-528000000 {
+			opp-hz = /bits/ 64 <528000000>;
+			opp-microvolt = <900000>;
+		};
+		opp-780000000 {
+			opp-hz = /bits/ 64 <780000000>;
+			opp-microvolt = <900000>;
+		};
+		opp-920000000 {
+			opp-hz = /bits/ 64 <920000000>;
+			opp-microvolt = <900000>;
+			status = "disabled";
+		};
+		opp-1560000000 {
+			opp-hz = /bits/ 64 <1560000000>;
+			opp-microvolt = <900000>;
+		};
+	};
+
 	pcie2x1: pcie@fe260000 {
 		compatible = "rockchip,rk3568-pcie", "snps,dw-pcie";
 		#address-cells = <3>;