From e116be010f7d09bfba7360b09687bf1ffd862b3c Mon Sep 17 00:00:00 2001 From: Xing Zheng Date: Sun, 24 Apr 2022 11:49:27 +0800 Subject: [PATCH] ASoC: codecs: rv1106_codec: fix some acodec handlings - Remove disable/enable ADC after put ADC mode - Makes the unity name for ACODEC_ADC_L(R)_DIG_VOL - Fixes ACODEC_ADC_L_WORK to ACODEC_ADC_R_WORK for right channel Signed-off-by: Xing Zheng Change-Id: I21912c96d9ed6954556983745f94ea0e1dbb6283 --- sound/soc/codecs/rv1106_codec.c | 5 +---- sound/soc/codecs/rv1106_codec.h | 14 ++++++++------ 2 files changed, 9 insertions(+), 10 deletions(-) diff --git a/sound/soc/codecs/rv1106_codec.c b/sound/soc/codecs/rv1106_codec.c index ae00033309f6..dc6bd0e8aaff 100644 --- a/sound/soc/codecs/rv1106_codec.c +++ b/sound/soc/codecs/rv1106_codec.c @@ -465,9 +465,6 @@ static int rv1106_codec_adc_mode_put(struct snd_kcontrol *kcontrol, return 0; } - rv1106_codec_adc_disable(rv1106); - rv1106_codec_adc_enable(rv1106); - return 0; } @@ -1437,7 +1434,7 @@ static int rv1106_codec_adc_enable(struct rv1106_codec_priv *rv1106) L(lr, ACODEC_ADC_L_WORK) | R(lr, ACODEC_ADC_R_WORK), L(lr, ACODEC_ADC_L_WORK) | - R(lr, ACODEC_ADC_L_WORK)); + R(lr, ACODEC_ADC_R_WORK)); /* vendor step 9 */ regmap_update_bits(rv1106->regmap, ACODEC_ADC_ANA_CTL6, diff --git a/sound/soc/codecs/rv1106_codec.h b/sound/soc/codecs/rv1106_codec.h index b9e17d312985..4ac18c8f88b5 100644 --- a/sound/soc/codecs/rv1106_codec.h +++ b/sound/soc/codecs/rv1106_codec.h @@ -19,8 +19,8 @@ #define ACODEC_DAC_I2S_CTL1 0x14 /* REG 0x05 */ #define ACODEC_DAC_GAIN_SEL 0x18 /* REG 0x06 */ #define ACODEC_DAC_L_BIST_MODE_SEL 0x1c /* REG 0x07 */ -#define ACODEC_ADC_L_DIGITAL_VOL_CTL 0x20 /* REG 0x08 */ -#define ACODEC_ADC_R_DGTL_VOL_CTL 0x24 /* REG 0x09 */ +#define ACODEC_ADC_L_DIG_VOL 0x20 /* REG 0x08 */ +#define ACODEC_ADC_R_DIG_VOL 0x24 /* REG 0x09 */ #define ACODEC_ADC_HPF_PGA_CTL 0x28 /* REG 0x0a */ #define ACODEC_INIT_DELAY_CNT1 0x2c /* REG 0x0b */ #define ACODEC_INIT_DELAY_CNT2 0x30 /* REG 0x0c */ @@ -194,11 +194,13 @@ #define ACODEC_DAC_L_CH_BIST_SINE (0x1 << ACODEC_DAC_L_CH_BIST_SFT) #define ACODEC_DAC_L_CH_BIST_LEFT (0x0 << ACODEC_DAC_L_CH_BIST_SFT) /* normal mode */ -/* ACODEC_ADC_L_DIGITAL_VOL_CTL */ -#define ACODEC_ADC_L_DIGITAL_MUTE 0x0 +/* ACODEC_ADC_L_DIG_VOL */ +#define ACODEC_ADC_L_DIG_VOL_MUTE 0 +#define ACODEC_ADC_L_DIG_VOL_0DB 0xc3 -/* ACODEC_ADC_R_DIGITAL_VOL_CTL */ -#define ACODEC_ADC_R_DIGITAL_MUTE 0x0 +/* ACODEC_ADC_R_DIG_VOL */ +#define ACODEC_ADC_R_DIG_VOL_MUTE 0 +#define ACODEC_ADC_R_DIG_VOL_0DB 0xc3 /* ACODEC_ADC_HPF_PGA_CTL */ #define ACODEC_ADC_FILTER_MSK (1 << 7)