diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 330798272f31..56d1ab379989 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1010,6 +1010,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
 	rk3066a-mk808.dtb \
 	rk3066a-rayeager.dtb \
 	rk3126c-evb-ddr3-v10-linux.dtb \
+	rk3126c-evb-ddr3-v10-linux-slc.dtb \
 	rk3188-bqedison2qc.dtb \
 	rk3188-px3-evb.dtb \
 	rk3188-radxarock.dtb \
diff --git a/arch/arm/boot/dts/rk3126c-evb-ddr3-v10-linux-slc.dts b/arch/arm/boot/dts/rk3126c-evb-ddr3-v10-linux-slc.dts
new file mode 100644
index 000000000000..7e81ff3dfabe
--- /dev/null
+++ b/arch/arm/boot/dts/rk3126c-evb-ddr3-v10-linux-slc.dts
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2022 Rockchip Electronics Co., Ltd
+ */
+/dts-v1/;
+#include "rk3126c-evb-ddr3-v10-linux.dts"
+/ {
+	chosen {
+		bootargs = "ubi.mtd=7 root=ubi0:rootfs rootfstype=ubifs";
+	};
+};
+
+&emmc {
+	status = "disabled";
+};
+
+&nandc {
+	status = "okay";
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	assigned-clocks = <&cru SCLK_NANDC>;
+	assigned-clock-rates = <120000000>;
+
+	nand@0 {
+		reg = <0>;
+		nand-bus-width = <8>;
+		nand-ecc-mode = "hw";
+		nand-ecc-strength = <16>;
+		nand-ecc-step-size = <1024>;
+	};
+};