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arm: dts: rockchip: add u2phy otg-port and dwc2 ctrl nodes for rk322x SoC

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This patch adds dwc2 controller and its phy nodes for rk322x SoC.

Change-Id: I29779baf92c28154ad342e234e8a5582984b8a12
Signed-off-by: William Wu <william.wu@rock-chips.com>
This commit is contained in:
William Wu
2017-05-05 17:29:56 +08:00
committed by Huang, Tao
parent 333afcb8a3
commit e183dc8bfd
1 changed files with 27 additions and 0 deletions
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27
arch/arm/boot/dts/rk322x.dtsi
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@@ -194,6 +194,16 @@
clock-output-names = "usb480m_phy0";
status = "disabled";
u2phy0_otg: otg-port {
#phy-cells = <0>;
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "otg-bvalid", "otg-id",
"linestate";
status = "disabled";
};
u2phy0_host: host-port {
#phy-cells = <0>;
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
@@ -494,6 +504,23 @@
status = "disabled";
};
usb_otg: usb@30040000 {
compatible = "rockchip,rk322x-usb", "rockchip,rk3066-usb",
"snps,dwc2";
reg = <0x30040000 0x40000>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_OTG>;
clock-names = "otg";
dr_mode = "otg";
g-np-tx-fifo-size = <16>;
g-rx-fifo-size = <275>;
g-tx-fifo-size = <256 128 128 64 64 32>;
g-use-dma;
phys = <&u2phy0_otg>;
phy-names = "usb2-phy";
status = "disabled";
};
usb_host0_ehci: usb@30080000 {
compatible = "generic-ehci";
reg = <0x30080000 0x20000>;