From e1f6d87fc5b41a5c7e4d007cf80ab68f04a40be6 Mon Sep 17 00:00:00 2001 From: Damon Ding Date: Wed, 16 Apr 2025 15:31:34 +0800 Subject: [PATCH] drm/bridge: analogix_dp: use &link_train.max_lane_count to determine the &link_train.lane_count Fixes: a20520933058 ("drm/bridge: analogix_dp: Add &link_train.max_link_rate and &link_train.max_lane_count") Change-Id: I9938e43bd37ddfc93838849c35dd2e76c8d31f0c Signed-off-by: Damon Ding --- drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c index c37201c4fb78..85f6f5df4f1a 100644 --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c @@ -889,7 +889,7 @@ static int analogix_dp_full_link_train(struct analogix_dp_device *dp, analogix_dp_reset_macro(dp); /* Setup TX lane count */ - dp->link_train.lane_count = min_t(u32, dp->link_train.lane_count, max_lanes); + dp->link_train.lane_count = min_t(u32, dp->link_train.max_lane_count, max_lanes); /* Setup TX lane rate */ if (analogix_dp_select_rx_bandwidth(dp)) {