From 43675f80cc8ef3c50226d02fc56f63e1a149a2a5 Mon Sep 17 00:00:00 2001 From: Zhihuan He Date: Tue, 28 May 2024 11:48:13 +0800 Subject: [PATCH 1/4] EDAC/rockchip: support ddr ecc poison Change-Id: If3746dee41d2717f3c3ce9e3caa5c53ac9d8ef84 Signed-off-by: Zhihuan He --- drivers/edac/rockchip_edac.c | 106 ++++++++++++++++++++++++++++ include/soc/rockchip/rockchip_sip.h | 1 + 2 files changed, 107 insertions(+) diff --git a/drivers/edac/rockchip_edac.c b/drivers/edac/rockchip_edac.c index 4b1317bed1d0..0824bf5246d2 100644 --- a/drivers/edac/rockchip_edac.c +++ b/drivers/edac/rockchip_edac.c @@ -5,8 +5,10 @@ #include #include +#include #include #include +#include #include #include "edac_module.h" @@ -42,6 +44,18 @@ #define ECC_UNCORR_BANK_MASK (0x7) #define ECC_UNCORR_COL_MASK (0xfff) +#define DDR_ECC_CE_DATA_POISON (1) +#define DDR_ECC_UE_DATA_POISON (0) + +#define DDR_ECC_POISON_EN (1) +#define DDR_ECC_POISON_DIS (0) + +/* [15:8]: high version + [7:0]: low version */ +#define DDR_ECC_CFG_VER (0x100) +#define DDR_ECC_CFG_VER_V101 (0x101) + +#define DDR_ECC_TAG_KERNEL (0x5588eedd) + /** * struct ddr_ecc_error_info - DDR ECC error log information * @err_cnt: error count @@ -74,6 +88,24 @@ struct ddr_ecc_status { struct ddr_ecc_error_info ueinfo; }; +/** + * struct rk_ddr_ecc_cfg - RK DDR ECC config + * @ecc_cfg_ver: version for DDR ECC config + * @ecc_poiso_en: enable ecc data poisoning + * @ecc_poison_mode: corrected/uncorrected data poisoning mode + * @ecc_poison_addr: DDR ECC Data Poisoning Address + */ +struct rk_ddr_ecc_cfg { + u32 ecc_cfg_ver; + u32 ecc_poison_en; + u32 ecc_poison_mode; + u64 ecc_poison_addr; + u64 ce_addr; + u64 ue_addr; + struct ddr_ecc_error_info poison; + u32 kernel_tag; +}; + /** * struct rk_edac_priv - RK DDR memory controller private instance data * @name: EDAC name @@ -93,6 +125,9 @@ struct rk_edac_priv { }; static struct ddr_ecc_status *ddr_edac_info; +static struct rk_ddr_ecc_cfg *ddr_edac_cfg; + +static char edac_poison_mode[4] = "ce"; static inline void opstate_init_int(void) { @@ -141,6 +176,37 @@ static void rockchip_edac_handle_ue_error(struct mem_ctl_info *mci, } } +static int rockchip_ddr_ecc_poison(struct rk_ddr_ecc_cfg *cfg) +{ + struct arm_smccc_res res; + + cfg->ecc_cfg_ver = DDR_ECC_CFG_VER_V101; + cfg->kernel_tag = DDR_ECC_TAG_KERNEL; + cfg->ecc_poison_en = DDR_ECC_POISON_EN; + + res = sip_smc_dram(SHARE_PAGE_TYPE_DDRECC, 0, + ROCKCHIP_SIP_CONFIG_DRAM_ECC_POISON); + if ((res.a0) || (res.a1)) { + edac_printk(KERN_ERR, EDAC_MC, + "ROCKCHIP_SIP_CONFIG_DRAM_ECC_POISON not support: 0x%lx-0x%lx\n", + res.a0, res.a1); + return -ENXIO; + } + + /* disable ddr ecc poison */ + cfg->ecc_poison_en = DDR_ECC_POISON_DIS; + res = sip_smc_dram(SHARE_PAGE_TYPE_DDRECC, 0, + ROCKCHIP_SIP_CONFIG_DRAM_ECC_POISON); + if ((res.a0) || (res.a1)) { + edac_printk(KERN_ERR, EDAC_MC, + "ROCKCHIP_SIP_CONFIG_DRAM_ECC_POISON not support: 0x%lx-0x%lx\n", + res.a0, res.a1); + return -ENXIO; + } + + return 0; +} + static int rockchip_edac_get_error_info(struct mem_ctl_info *mci) { struct arm_smccc_res res; @@ -205,6 +271,36 @@ static irqreturn_t rockchip_edac_mc_ue_isr(int irq, void *dev_id) return IRQ_HANDLED; } +static int rockchip_edac_trigger(const char *val, const struct kernel_param *kp) +{ + int ret = 0; + unsigned long value, i; + + if (ddr_edac_cfg == NULL) + return -1; + + if (kstrtoul(val, 0, &value) < 0) + return 0; + + if (!strncmp(edac_poison_mode, "ce", 2)) { + ddr_edac_cfg->ecc_poison_mode = DDR_ECC_CE_DATA_POISON; + } else if (!strncmp(edac_poison_mode, "ue", 2)) { + ddr_edac_cfg->ecc_poison_mode = DDR_ECC_UE_DATA_POISON; + } else { + ddr_edac_cfg->ecc_poison_mode = DDR_ECC_CE_DATA_POISON; + edac_printk(KERN_WARNING, EDAC_MC, + "unknown poison mode, used default mode: ce!\n"); + } + + for (i = 0; i < value; i++) { + rockchip_dmcfreq_lock(); + ret = rockchip_ddr_ecc_poison(ddr_edac_cfg); + rockchip_dmcfreq_unlock(); + } + + return ret; +} + static int rockchip_edac_mc_init(struct mem_ctl_info *mci, struct platform_device *pdev) { @@ -236,6 +332,9 @@ static int rockchip_edac_mc_init(struct mem_ctl_info *mci, ddr_edac_info = (struct ddr_ecc_status *)res.a1; memset(ddr_edac_info, 0, sizeof(struct ddr_ecc_status)); + ddr_edac_cfg = (struct rk_ddr_ecc_cfg *)(res.a1 + (4096 / 4)); + memset(ddr_edac_cfg, 0, sizeof(struct rk_ddr_ecc_cfg)); + ret = rockchip_edac_get_error_info(mci); if (ret) return ret; @@ -353,6 +452,13 @@ static struct platform_driver rockchip_edac_driver = { }; module_platform_driver(rockchip_edac_driver); +module_param_string(edac_poison_mode, edac_poison_mode, sizeof(edac_poison_mode), 0664); +MODULE_PARM_DESC(edac_poison_mode, "RK EDAC DDR ECC poison mode(ce or ue)."); + +module_param_call(rockchip_edac_trigger, rockchip_edac_trigger, NULL, NULL, 0664); +MODULE_PARM_DESC(rockchip_edac_trigger, + "RK EDAC DDR ECC triggered by writing the number of errors(greater than 0)."); + MODULE_LICENSE("GPL"); MODULE_AUTHOR("He Zhihuan \n"); MODULE_DESCRIPTION("ROCKCHIP EDAC kernel module"); diff --git a/include/soc/rockchip/rockchip_sip.h b/include/soc/rockchip/rockchip_sip.h index 269cf14c38fb..fafe6abe0d36 100644 --- a/include/soc/rockchip/rockchip_sip.h +++ b/include/soc/rockchip/rockchip_sip.h @@ -24,5 +24,6 @@ #define ROCKCHIP_SIP_CONFIG_DRAM_GET_FREQ_INFO 0x0e #define ROCKCHIP_SIP_CONFIG_DRAM_ADDRMAP_GET 0x10 #define ROCKCHIP_SIP_CONFIG_DRAM_GET_STALL_TIME 0x11 +#define ROCKCHIP_SIP_CONFIG_DRAM_ECC_POISON 0x12 #endif From f5f09fbd44a5d44ff839beffe5b488c67eb34d52 Mon Sep 17 00:00:00 2001 From: Shawn Lin Date: Wed, 12 Jun 2024 16:06:06 +0800 Subject: [PATCH 2/4] mmc: dw_mmc-rockchip: Fix internal phase calculate ciu clock from CRU is 2 times of interface clock, so the delay number maybe not so accurate as the sample phase is based on interface clock. Change-Id: Ib8d66f1c7af18fa3888dafc4528a95aabfa8572f Fixes: 1505eda5b9d2 ("mmc: dw_mmc-rockchip: Add internal phase support") Signed-off-by: Shawn Lin --- drivers/mmc/host/dw_mmc-rockchip.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/host/dw_mmc-rockchip.c b/drivers/mmc/host/dw_mmc-rockchip.c index 6a39dac56f2d..2e0bd74f4030 100644 --- a/drivers/mmc/host/dw_mmc-rockchip.c +++ b/drivers/mmc/host/dw_mmc-rockchip.c @@ -48,7 +48,7 @@ struct dw_mci_rockchip_priv_data { */ static int rockchip_mmc_get_phase(struct dw_mci *host, bool sample) { - unsigned long rate = clk_get_rate(host->ciu_clk); + unsigned long rate = clk_get_rate(host->ciu_clk) / RK3288_CLKGEN_DIV; u32 raw_value; u16 degrees; u32 delay_num = 0; @@ -79,7 +79,7 @@ static int rockchip_mmc_get_phase(struct dw_mci *host, bool sample) static int rockchip_mmc_set_phase(struct dw_mci *host, bool sample, int degrees) { - unsigned long rate = clk_get_rate(host->ciu_clk); + unsigned long rate = clk_get_rate(host->ciu_clk) / RK3288_CLKGEN_DIV; u8 nineties, remainder; u8 delay_num; u32 raw_value; From cfd0cc7ba657c8e76124a533e58181d1826ea83f Mon Sep 17 00:00:00 2001 From: Wu Liangqing Date: Wed, 12 Jun 2024 11:02:28 +0800 Subject: [PATCH 3/4] arm64: dts: rockchip: rk3562: rockchip_suspend disabled sleep debug Change-Id: Id73d07cbd1d99704f2f6ad63ee340ef0f2b6fd1c Signed-off-by: Wu Liangqing --- arch/arm64/boot/dts/rockchip/rk3562.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3562.dtsi b/arch/arm64/boot/dts/rockchip/rk3562.dtsi index 31c3699ef7d9..3ed54f3a7859 100644 --- a/arch/arm64/boot/dts/rockchip/rk3562.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3562.dtsi @@ -3048,7 +3048,7 @@ rockchip_suspend: rockchip-suspend { compatible = "rockchip,pm-rk3562"; status = "disabled"; - rockchip,sleep-debug-en = <1>; + rockchip,sleep-debug-en = <0>; rockchip,sleep-mode-config = < (0 | RKPM_SLP_DEEP1_MODE From a4c81b775b462ac0362e0672516c94f65989a8a6 Mon Sep 17 00:00:00 2001 From: Xing Zheng Date: Tue, 11 Jun 2024 15:22:14 +0800 Subject: [PATCH 4/4] ASoC: es8323: recover L/R stereo input and disable capture ALC and NG by default Generally speaking, the codec needs to ensure the normal input of left and right channels independently. If you want to forcethe duplication of channels, you can configure it through the control node in the user layer. Enabling ALC NG here will cause the sound pickup effect to be unstable. And, the default public version does not need to turn on the ALC NG function, so as not to introduce non-linear processing to the backend algorithm and cause unnecessary confusion to developers. Change-Id: I52e376c7d992d4bd08e863134b4c596cbfccbe2b Signed-off-by: Xing Zheng --- sound/soc/codecs/es8323.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/sound/soc/codecs/es8323.c b/sound/soc/codecs/es8323.c index f811c3367386..ed7416411a7d 100644 --- a/sound/soc/codecs/es8323.c +++ b/sound/soc/codecs/es8323.c @@ -770,17 +770,17 @@ static int es8323_probe(struct snd_soc_component *component) snd_soc_component_write(component, 0x06, 0xC3); snd_soc_component_write(component, 0x19, 0x02); snd_soc_component_write(component, 0x09, 0x00); - snd_soc_component_write(component, 0x0A, 0x00); - snd_soc_component_write(component, 0x0B, 0x02); - snd_soc_component_write(component, 0x0C, 0x4C); + snd_soc_component_write(component, 0x0A, 0xf8); + snd_soc_component_write(component, 0x0B, 0x82); + snd_soc_component_write(component, 0x0C, 0x0C); snd_soc_component_write(component, 0x0D, 0x02); snd_soc_component_write(component, 0x10, 0x00); snd_soc_component_write(component, 0x11, 0x00); - snd_soc_component_write(component, 0x12, 0xea); + snd_soc_component_write(component, 0x12, 0x00); snd_soc_component_write(component, 0x13, 0xc0); snd_soc_component_write(component, 0x14, 0x05); snd_soc_component_write(component, 0x15, 0x06); - snd_soc_component_write(component, 0x16, 0x53); + snd_soc_component_write(component, 0x16, 0x52); snd_soc_component_write(component, 0x17, 0x18); snd_soc_component_write(component, 0x18, 0x02);