diff --git a/drivers/clk/rockchip/clk-rk3588.c b/drivers/clk/rockchip/clk-rk3588.c index df851a55a21b..76a2f3262f99 100644 --- a/drivers/clk/rockchip/clk-rk3588.c +++ b/drivers/clk/rockchip/clk-rk3588.c @@ -93,13 +93,14 @@ static struct rockchip_pll_rate_table rk3588_pll_rates[] = { #define RK3588_CLK_CORE_B0_GPLL_DIV_MASK 0x1f #define RK3588_CLK_CORE_B0_GPLL_DIV_SHIFT 1 #define RK3588_CLK_CORE_L_SEL_CLEAN_MASK 0x3 -#define RK3588_CLK_CORE_L_SEL_CLEAN_SHIFT 5 +#define RK3588_CLK_CORE_L1_SEL_CLEAN_SHIFT 12 +#define RK3588_CLK_CORE_L0_SEL_CLEAN_SHIFT 5 #define RK3588_CLK_DSU_SEL_DF_MASK 0x1 #define RK3588_CLK_DSU_SEL_DF_SHIFT 15 #define RK3588_CLK_DSU_DF_SRC_MASK 0x3 -#define RK3588_CLK_DSU_DF_SRC_SHIFT 5 +#define RK3588_CLK_DSU_DF_SRC_SHIFT 12 #define RK3588_CLK_DSU_DF_DIV_MASK 0x1f -#define RK3588_CLK_DSU_DF_DIV_SHIFT 0 +#define RK3588_CLK_DSU_DF_DIV_SHIFT 7 #define RK3588_ACLKM_DSU_DIV_MASK 0x1f #define RK3588_ACLKM_DSU_DIV_SHIFT 1 #define RK3588_ACLKS_DSU_DIV_MASK 0x1f @@ -149,9 +150,9 @@ static struct rockchip_pll_rate_table rk3588_pll_rates[] = { { \ .reg = RK3588_DSU_CLKSEL_CON(6 + _offs), \ .val = HIWORD_UPDATE(_apllcore, RK3588_CLK_CORE_L_SEL_CLEAN_MASK, \ - RK3588_CLK_CORE_L_SEL_CLEAN_SHIFT) | \ + RK3588_CLK_CORE_L0_SEL_CLEAN_SHIFT) | \ HIWORD_UPDATE(_apllcore, RK3588_CLK_CORE_L_SEL_CLEAN_MASK, \ - RK3588_CLK_CORE_L_SEL_CLEAN_SHIFT), \ + RK3588_CLK_CORE_L1_SEL_CLEAN_SHIFT), \ } #define RK3588_CORE_L_SEL1(_seldsu, _divdsu) \ @@ -160,9 +161,7 @@ static struct rockchip_pll_rate_table rk3588_pll_rates[] = { .val = HIWORD_UPDATE(_seldsu, RK3588_CLK_DSU_DF_SRC_MASK, \ RK3588_CLK_DSU_DF_SRC_SHIFT) | \ HIWORD_UPDATE(_divdsu - 1, RK3588_CLK_DSU_DF_DIV_MASK, \ - RK3588_CLK_DSU_DF_DIV_SHIFT) | \ - HIWORD_UPDATE(0, RK3588_CLK_DSU_SEL_DF_MASK, \ - RK3588_CLK_DSU_SEL_DF_SHIFT), \ + RK3588_CLK_DSU_DF_DIV_SHIFT), \ } #define RK3588_CORE_L_SEL2(_aclkm, _aclkmp, _aclks) \ @@ -222,7 +221,7 @@ static struct rockchip_pll_rate_table rk3588_pll_rates[] = { .pre_muxs = { \ RK3588_CORE_L_SEL0(0, 0), \ RK3588_CORE_L_SEL0(1, 0), \ - RK3588_CORE_L_SEL1(3, 2), \ + RK3588_CORE_L_SEL1(3, 4), \ }, \ .post_muxs = { \ RK3588_CORE_L_SEL0(0, _apllcore), \ @@ -346,41 +345,41 @@ static const struct rockchip_cpuclk_reg_data rk3588_cpub1clk_data = { }; static struct rockchip_cpuclk_rate_table rk3588_cpulclk_rates[] __initdata = { - RK3588_CPULCLK_RATE(2208000000, 1, 3, 1, 4, 4, 4, 4, 4, 4), - RK3588_CPULCLK_RATE(2184000000, 1, 3, 1, 4, 4, 4, 4, 4, 4), - RK3588_CPULCLK_RATE(2088000000, 1, 3, 1, 4, 4, 4, 4, 4, 4), - RK3588_CPULCLK_RATE(2040000000, 1, 3, 1, 4, 4, 4, 4, 4, 4), - RK3588_CPULCLK_RATE(2016000000, 1, 3, 1, 4, 4, 4, 4, 4, 4), - RK3588_CPULCLK_RATE(1992000000, 1, 3, 1, 4, 4, 4, 4, 4, 4), - RK3588_CPULCLK_RATE(1896000000, 1, 3, 1, 4, 4, 4, 4, 4, 4), - RK3588_CPULCLK_RATE(1800000000, 1, 3, 1, 4, 4, 4, 4, 4, 4), - RK3588_CPULCLK_RATE(1704000000, 0, 3, 1, 3, 3, 3, 3, 3, 3), - RK3588_CPULCLK_RATE(1608000000, 0, 3, 1, 3, 3, 3, 2, 3, 3), - RK3588_CPULCLK_RATE(1584000000, 0, 3, 1, 3, 3, 3, 2, 3, 3), - RK3588_CPULCLK_RATE(1560000000, 0, 2, 2, 3, 3, 3, 2, 3, 3), - RK3588_CPULCLK_RATE(1536000000, 0, 2, 2, 3, 3, 3, 2, 3, 3), - RK3588_CPULCLK_RATE(1512000000, 0, 2, 2, 3, 3, 3, 2, 3, 3), - RK3588_CPULCLK_RATE(1488000000, 0, 2, 2, 3, 3, 3, 2, 3, 3), - RK3588_CPULCLK_RATE(1464000000, 0, 2, 2, 3, 3, 3, 2, 3, 3), - RK3588_CPULCLK_RATE(1440000000, 0, 2, 2, 3, 3, 3, 2, 3, 3), - RK3588_CPULCLK_RATE(1416000000, 0, 2, 2, 3, 3, 3, 2, 3, 3), - RK3588_CPULCLK_RATE(1392000000, 0, 2, 2, 3, 3, 3, 2, 3, 3), - RK3588_CPULCLK_RATE(1368000000, 0, 2, 2, 3, 3, 3, 2, 3, 3), - RK3588_CPULCLK_RATE(1344000000, 0, 2, 2, 3, 3, 3, 2, 3, 3), - RK3588_CPULCLK_RATE(1320000000, 0, 2, 2, 3, 3, 3, 2, 3, 3), - RK3588_CPULCLK_RATE(1296000000, 0, 2, 2, 3, 3, 3, 2, 3, 3), - RK3588_CPULCLK_RATE(1272000000, 0, 2, 2, 2, 2, 2, 2, 2, 2), - RK3588_CPULCLK_RATE(1248000000, 0, 2, 2, 2, 2, 2, 2, 2, 2), - RK3588_CPULCLK_RATE(1224000000, 0, 2, 2, 2, 2, 2, 2, 2, 2), - RK3588_CPULCLK_RATE(1200000000, 0, 2, 2, 2, 2, 2, 2, 2, 2), - RK3588_CPULCLK_RATE(1104000000, 0, 2, 2, 2, 2, 2, 2, 2, 2), - RK3588_CPULCLK_RATE(1008000000, 0, 2, 2, 2, 2, 2, 2, 2, 2), - RK3588_CPULCLK_RATE(912000000, 0, 2, 2, 2, 2, 2, 1, 2, 2), + RK3588_CPULCLK_RATE(2208000000, 1, 3, 1, 4, 4, 4, 4, 4, 6), + RK3588_CPULCLK_RATE(2184000000, 1, 3, 1, 4, 4, 4, 4, 4, 6), + RK3588_CPULCLK_RATE(2088000000, 1, 3, 1, 4, 4, 4, 4, 4, 6), + RK3588_CPULCLK_RATE(2040000000, 1, 3, 1, 4, 4, 4, 4, 4, 6), + RK3588_CPULCLK_RATE(2016000000, 1, 3, 1, 4, 4, 4, 4, 4, 5), + RK3588_CPULCLK_RATE(1992000000, 1, 3, 1, 4, 4, 4, 4, 4, 5), + RK3588_CPULCLK_RATE(1896000000, 1, 3, 1, 4, 4, 4, 4, 4, 5), + RK3588_CPULCLK_RATE(1800000000, 1, 3, 1, 4, 4, 4, 4, 4, 5), + RK3588_CPULCLK_RATE(1704000000, 0, 3, 1, 4, 4, 4, 3, 4, 5), + RK3588_CPULCLK_RATE(1608000000, 0, 3, 1, 4, 4, 4, 3, 4, 5), + RK3588_CPULCLK_RATE(1584000000, 0, 3, 1, 4, 4, 4, 3, 4, 5), + RK3588_CPULCLK_RATE(1560000000, 0, 2, 2, 4, 4, 4, 3, 4, 5), + RK3588_CPULCLK_RATE(1536000000, 0, 2, 2, 4, 4, 4, 3, 4, 5), + RK3588_CPULCLK_RATE(1512000000, 0, 2, 2, 4, 4, 4, 2, 4, 5), + RK3588_CPULCLK_RATE(1488000000, 0, 2, 2, 4, 4, 4, 2, 4, 5), + RK3588_CPULCLK_RATE(1464000000, 0, 2, 2, 4, 4, 4, 2, 4, 5), + RK3588_CPULCLK_RATE(1440000000, 0, 2, 2, 3, 3, 3, 2, 3, 4), + RK3588_CPULCLK_RATE(1416000000, 0, 2, 2, 3, 3, 3, 2, 3, 4), + RK3588_CPULCLK_RATE(1392000000, 0, 2, 2, 3, 3, 3, 2, 3, 4), + RK3588_CPULCLK_RATE(1368000000, 0, 2, 2, 3, 3, 3, 2, 3, 4), + RK3588_CPULCLK_RATE(1344000000, 0, 2, 2, 3, 3, 3, 2, 3, 4), + RK3588_CPULCLK_RATE(1320000000, 0, 2, 2, 3, 3, 3, 2, 3, 4), + RK3588_CPULCLK_RATE(1296000000, 0, 2, 2, 3, 3, 3, 2, 3, 4), + RK3588_CPULCLK_RATE(1272000000, 0, 2, 2, 3, 3, 3, 2, 3, 3), + RK3588_CPULCLK_RATE(1248000000, 0, 2, 2, 3, 3, 3, 2, 3, 3), + RK3588_CPULCLK_RATE(1224000000, 0, 2, 2, 3, 3, 3, 2, 3, 3), + RK3588_CPULCLK_RATE(1200000000, 0, 2, 2, 3, 3, 3, 2, 3, 3), + RK3588_CPULCLK_RATE(1104000000, 0, 2, 2, 2, 2, 2, 2, 2, 3), + RK3588_CPULCLK_RATE(1008000000, 0, 2, 2, 2, 2, 2, 2, 2, 3), + RK3588_CPULCLK_RATE(912000000, 0, 2, 2, 2, 2, 2, 2, 2, 3), RK3588_CPULCLK_RATE(816000000, 0, 2, 2, 2, 2, 2, 1, 2, 2), RK3588_CPULCLK_RATE(696000000, 0, 2, 2, 2, 2, 2, 1, 2, 2), - RK3588_CPULCLK_RATE(600000000, 0, 2, 1, 1, 1, 1, 1, 1, 1), - RK3588_CPULCLK_RATE(408000000, 0, 2, 1, 1, 1, 1, 1, 1, 1), - RK3588_CPULCLK_RATE(312000000, 0, 2, 1, 1, 1, 1, 1, 1, 1), + RK3588_CPULCLK_RATE(600000000, 0, 2, 2, 2, 2, 2, 1, 2, 2), + RK3588_CPULCLK_RATE(408000000, 0, 2, 2, 2, 2, 2, 1, 2, 2), + RK3588_CPULCLK_RATE(312000000, 0, 2, 2, 2, 2, 2, 1, 2, 2), RK3588_CPULCLK_RATE(216000000, 0, 2, 1, 1, 1, 1, 1, 1, 1), RK3588_CPULCLK_RATE(96000000, 0, 2, 1, 1, 1, 1, 1, 1, 1), };