diff --git a/arch/arm64/boot/dts/rockchip/rk3576-eink.dtsi b/arch/arm64/boot/dts/rockchip/rk3576-eink.dtsi index c615ded870f8..c8c75f842ae1 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-eink.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576-eink.dtsi @@ -78,6 +78,30 @@ shutdown_temperture_threshold = <160>; hotdie_temperture_threshold = <115>; + /* The entered value specifies the delay time (in milliseconds) + * that the PMIC waits after receiving the shutdown signal + * before executing the power-off action. + */ + shutdown-sequence = <2 2 2 0 2 0 2 1 1 2 + 2 2 2 2 2 + 1 0 0 0 0 2>; + + /* low power forced shutdown sequence */ + vb-shutdown-sequence = <2 2 2 0 2 0 2 0 0 2 + 2 2 2 2 2 + 0 0 0 0 0 2>; + /* DVS control: + * This configuration is tightly bound to the hardware + * and requires ATF (Arm Trusted Firmware) support + * 0: no effect + * 1: controlled by PWRCTRL1 + * 2: controlled by PWRCTRL2 + * 3: controlled by PWRCTRL3 + */ + dvs-suspend-control-by = <0 0 0 0 0 2 0 0 0 2 + 0 0 2 0 0 + 2 2 0 0 0 0>; + /* 0: restart PMU; * 1: reset all the power off reset registers, * forcing the state to switch to ACTIVE mode; diff --git a/arch/arm64/boot/dts/rockchip/rk3576-evb-input-keymap.dtsi b/arch/arm64/boot/dts/rockchip/rk3576-evb-input-keymap.dtsi index 2161be2124bd..6f3002bd7b66 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-evb-input-keymap.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576-evb-input-keymap.dtsi @@ -4,6 +4,8 @@ * */ +#include + &pwm0_2ch_0 { compatible = "rockchip,remotectl-pwm-v4"; pinctrl-names = "default"; @@ -14,33 +16,6 @@ status = "okay"; ir_key1 { - rockchip,usercode = <0x4040>; - rockchip,key_table = - <0xf2 KEY_REPLY>, - <0xba KEY_BACK>, - <0xf4 KEY_UP>, - <0xf1 KEY_DOWN>, - <0xef KEY_LEFT>, - <0xee KEY_RIGHT>, - <0xbd KEY_HOME>, - <0xea KEY_VOLUMEUP>, - <0xe3 KEY_VOLUMEDOWN>, - <0xe2 KEY_SEARCH>, - <0xb2 KEY_POWER>, - <0xbc KEY_MUTE>, - <0xec KEY_MENU>, - <0xbf 0x190>, - <0xe0 0x191>, - <0xe1 0x192>, - <0xe9 183>, - <0xe6 248>, - <0xe8 185>, - <0xe7 186>, - <0xf0 388>, - <0xbe 0x175>; - }; - - ir_key2 { rockchip,usercode = <0xff00>; rockchip,key_table = <0xb1 KEY_HOME>, @@ -65,15 +40,77 @@ <0xe8 388>, <0xf8 184>, <0xaf 185>, - <0xed KEY_VOLUMEDOWN>, - <0xee 186>, - <0xb3 KEY_VOLUMEDOWN>, <0xf1 KEY_VOLUMEDOWN>, <0xf2 KEY_VOLUMEDOWN>, <0xf3 KEY_SEARCH>, <0xb4 KEY_VOLUMEDOWN>, <0xa4 KEY_SETUP>, - <0xbe KEY_SEARCH>; + <0xb0 KEY_SETUP>, + <0xbe KEY_SEARCH>, + <0xf0 KEY_1>, + <0xee KEY_2>, + <0xed KEY_3>, + <0xb3 KEY_4>, + <0xa7 KEY_5>, + <0xe4 KEY_6>, + <0xe8 KEY_6>, + <0xb2 KEY_8>, + <0xf5 KEY_9>, + <0xe2 KEY_0>; + }; + + /*for IPTV ltjc*/ + ir_key2 { + rockchip,usercode = <0xc43b>; + rockchip,key_table = + <0x7e KEY_REPLY>, + <0x7f KEY_BACK>, + <0x7a KEY_UP>, + <0x78 KEY_DOWN>, + <0x7b KEY_LEFT>, + <0x79 KEY_RIGHT>, + <0x66 KEY_VOLUMEUP>, + <0x65 KEY_VOLUMEDOWN>, + <0x69 KEY_POWER>, + <0x64 KEY_MUTE>, + <0x76 KEY_1>, + <0x75 KEY_2>, + <0x74 KEY_3>, + <0x73 KEY_4>, + <0x72 KEY_5>, + <0x71 KEY_6>, + <0x70 KEY_7>, + <0x6f KEY_8>, + <0x6e KEY_9>, + <0x77 KEY_0>, + <0x7c KEY_PAGEDOWN>, + <0x7d KEY_PAGEUP>, + <0x6a KEY_SETUP>, + <0x68 KEY_CHANNEL_UP>, + <0x67 KEY_CHANNEL_DN>, + <0x39 KEY_PORTAL>, + <0x29 KEY_HOME_PAGE>, + <0x33 KEY_CH_CUT_BACK>, + <0x34 KEY_LOCAL>, + <0x2d KEY_REVIEW>, + <0x2c KEY_ON_DEMAND>, + <0x2b KEY_INFO1>, + <0x2e KEY_DIRECT_SEEDING>, + <0x2d KEY_REVIEW>, + <0x2c KEY_ON_DEMAND>, + <0x2b KEY_INFO1>, + <0x63 KEY_SOUND1>, + <0x6c KEY_X1>, + <0x6d KEY_X2>, + <0x62 KEY_PLAYPAUSE>, + <0x6b KEY_EQUAL>, + <0x61 KEY_FASTFORWARD>, + <0x60 KEY_REWIND>, + <0x3b KEY_STOP>, + <0x35 KEY_BLUE>, + <0x36 KEY_YELLOW>, + <0x37 KEY_GREEN>, + <0x38 KEY_RED>; }; ir_key3 { @@ -107,5 +144,270 @@ <0xb6 KEY_0>, <0xb5 KEY_BACKSPACE>; }; + + /* for IPTV */ + ir_key4 { + rockchip,usercode = <0x4db2>; + rockchip,key_table = + <0x31 KEY_REPLY>, + <0x3a KEY_BACK>, + <0x35 KEY_UP>, + <0x2d KEY_DOWN>, + <0x66 KEY_LEFT>, + <0x3e KEY_RIGHT>, + <0x7f KEY_VOLUMEUP>, + <0xfe KEY_VOLUMEDOWN>, + <0x23 KEY_POWER>, + <0x63 KEY_MUTE>, + <0x6d KEY_1>, + <0x6c KEY_2>, + <0x33 KEY_3>, + <0x71 KEY_4>, + <0x70 KEY_5>, + <0x37 KEY_6>, + <0x75 KEY_7>, + <0x74 KEY_8>, + <0x3b KEY_9>, + <0x78 KEY_0>, + <0x73 KEY_PAGEDOWN>, + <0x22 KEY_PAGEUP>, + <0x72 KEY_SETUP>, + <0x7a KEY_CHANNEL_UP>, + <0x79 KEY_CHANNEL_DN>, + <0x77 KEY_HOME_PAGE>, + <0x29 KEY_CH_CUT_BACK>, + <0x32 KEY_DIRECT_SEEDING>, + <0x6e KEY_REVIEW>, + <0x7c KEY_ON_DEMAND>, + <0x3c KEY_INFO1>, + <0x67 KEY_SOUND1>, + <0x25 KEY_X1>, + <0x2f KEY_X2>, + <0x7d KEY_LOCAL>, + <0x6a KEY_PLAYPAUSE>, + <0x0b KEY_EQUAL>; + }; + + /* for CMCC */ + ir_key5 { + rockchip,usercode = <0x1608>; + rockchip,key_table = + <0x4c KEY_REPLY>, + <0x4d KEY_BACK>, + <0x4b KEY_UP>, + <0x4a KEY_DOWN>, + <0x49 KEY_LEFT>, + <0x48 KEY_RIGHT>, + <0x4e KEY_HOME>, + <0x0b KEY_VOLUMEUP>, + <0x0c KEY_VOLUMEDOWN>, + <0x23 KEY_POWER>, + <0x45 KEY_MUTE>, + <0x44 KEY_MENU>, + <0x78 KEY_1>, + <0x77 KEY_2>, + <0x76 KEY_3>, + <0x75 KEY_4>, + <0x74 KEY_5>, + <0x73 KEY_6>, + <0x72 KEY_7>, + <0x71 KEY_8>, + <0x70 KEY_9>, + <0x79 KEY_0>, + <0x43 KEY_EQUAL>, + <0x72 KEY_X1>, + <0x5f KEY_SETUP>, + <0x25 KEY_DIRECT_SEEDING>, + <0x24 KEY_REVIEW>, + <0x21 KEY_ON_DEMAND>, + <0x20 KEY_INFO1>; + }; + + /* rk new remote */ + ir_key6 { + rockchip,usercode = <0xfe01>; + rockchip,key_table = + <0xec KEY_REPLY>, + <0xe6 KEY_BACK>, + <0xe9 KEY_UP>, + <0xe5 KEY_DOWN>, + <0xae KEY_LEFT>, + <0xaf KEY_RIGHT>, + <0xee KEY_HOME>, + <0xe7 KEY_VOLUMEUP>, + <0xef KEY_VOLUMEDOWN>, + <0xbf KEY_POWER>, + <0xbe KEY_MUTE>, + <0xb3 KEY_MENU>, + <0xff 388>, + <0xb1 KEY_1>, + <0xf2 KEY_2>, + <0xf3 KEY_3>, + <0xb5 KEY_4>, + <0xf6 KEY_5>, + <0xf7 KEY_6>, + <0xb9 KEY_7>, + <0xfa KEY_8>, + <0xfb KEY_9>, + <0xfe KEY_0>, + <0xbd KEY_EQUAL>, + <0xbc KEY_SETUP>, + <0xf0 KEY_LOCAL>, + <0x0d KEY_DIRECT_SEEDING>, + <0x0c KEY_REVIEW>, + <0x0b KEY_ON_DEMAND>, + <0x0a KEY_INFO1>, + <0x0e KEY_CH_CUT_BACK>; + }; + + /* for IPTV gd */ + ir_key7 { + rockchip,usercode = <0x4cb3>; + rockchip,key_table = + <0x31 KEY_REPLY>, + <0x3a KEY_BACK>, + <0x35 KEY_UP>, + <0x2d KEY_DOWN>, + <0x66 KEY_LEFT>, + <0x3e KEY_RIGHT>, + <0x7f KEY_VOLUMEUP>, + <0x7e KEY_VOLUMEDOWN>, + <0x23 KEY_POWER>, + <0x63 KEY_MUTE>, + <0x6d KEY_1>, + <0x6c KEY_2>, + <0x33 KEY_3>, + <0x71 KEY_4>, + <0x70 KEY_5>, + <0x37 KEY_6>, + <0x75 KEY_7>, + <0x74 KEY_8>, + <0x3b KEY_9>, + <0x78 KEY_0>, + <0x73 KEY_PAGEDOWN>, + <0x22 KEY_PAGEUP>, + <0x72 KEY_SETUP>, + <0x7a KEY_CHANNEL_UP>, + <0x79 KEY_CHANNEL_DN>, + <0x77 KEY_HOME_PAGE>, + <0x29 KEY_CH_CUT_BACK>, + <0x32 KEY_DIRECT_SEEDING>, + <0x6e KEY_REVIEW>, + <0x7c KEY_ON_DEMAND>, + <0x3c KEY_INFO1>, + <0x67 KEY_SOUND1>, + <0x25 KEY_X1>, + <0x2f KEY_X2>, + <0x7d KEY_LOCAL>, + <0x6a KEY_PLAYPAUSE>, + <0x0b KEY_EQUAL>; + }; + + /* for CMCC */ + ir_key8 { + rockchip,usercode = <0xdd22>; + rockchip,key_table = + <0x31 KEY_REPLY>, + <0x6a KEY_BACK>, + <0x35 KEY_UP>, + <0x2d KEY_DOWN>, + <0x66 KEY_LEFT>, + <0x3e KEY_RIGHT>, + <0x7f KEY_VOLUMEUP>, + <0x7e KEY_VOLUMEDOWN>, + <0x23 KEY_POWER>, + <0x63 KEY_MUTE>, + <0x6d KEY_1>, + <0x6c KEY_2>, + <0x33 KEY_3>, + <0x71 KEY_4>, + <0x70 KEY_5>, + <0x37 KEY_6>, + <0x75 KEY_7>, + <0x74 KEY_8>, + <0x3b KEY_9>, + <0x78 KEY_0>, + <0x73 KEY_PAGEDOWN>, + <0x22 KEY_PAGEUP>, + <0x72 KEY_SETUP>, + <0x7a KEY_CHANNEL_UP>, + <0x79 KEY_CHANNEL_DN>, + <0x77 KEY_HOME_PAGE>, + <0x2f KEY_CH_CUT_BACK>, + <0x32 KEY_DIRECT_SEEDING>, + <0x6e KEY_REVIEW>, + <0x7c KEY_ON_DEMAND>, + <0x3c KEY_INFO1>, + <0x3a KEY_HELP>, + <0x67 KEY_SOUND1>, + <0x25 KEY_X2>, + <0x7d KEY_MENU>, + <0x3f KEY_EQUAL>, + <0x29 388>, + <0x26 KEY_PLAYPAUSE>, + <0x76 401>, + <0x7b 400>, + <0x69 66>; + }; + + /* for BJLT IPTV */ + ir_key9 { + rockchip,usercode = <0x3bc4>; + rockchip,key_table = + <0x81 KEY_REPLY>, + <0x80 KEY_BACK>, + <0x85 KEY_UP>, + <0x87 KEY_DOWN>, + <0x84 KEY_LEFT>, + <0x86 KEY_RIGHT>, + <0x99 KEY_VOLUMEUP>, + <0x9a KEY_VOLUMEDOWN>, + <0x96 KEY_POWER>, + <0x9b KEY_MUTE>, + <0x89 KEY_1>, + <0x8a KEY_2>, + <0x8b KEY_3>, + <0x8c KEY_4>, + <0x8d KEY_5>, + <0x8e KEY_6>, + <0x8f KEY_7>, + <0x90 KEY_8>, + <0x91 KEY_9>, + <0x88 KEY_0>, + <0x83 KEY_PAGEDOWN>, + <0x82 KEY_PAGEUP>, + <0x95 KEY_SETUP>, + <0x97 KEY_CHANNEL_UP>, + <0x98 KEY_CHANNEL_DN>, + <0xc6 KEY_LOCAL>, + <0xd6 KEY_HOME_PAGE>, + <0xd7 KEY_TRACK>, + <0xcc KEY_CH_CUT_BACK>, + <0xc3 KEY_INTERX>, + <0xd1 KEY_DIRECT_SEEDING>, + <0xd2 KEY_REVIEW>, + <0xd3 KEY_ON_DEMAND>, + <0xd4 KEY_INFO1>, + <0xc7 KEY_DIRECT_SEEDING>, + <0xc8 KEY_REVIEW>, + <0xc9 KEY_ON_DEMAND>, + <0xca KEY_INFO1>, + <0xcd KEY_FAVORITE>, + <0xce KEY_CHANNEL_POS>, + <0xcf KEY_HELP>, + <0xd0 KEY_EVENT>, + <0x9c KEY_SOUND1>, + <0x93 KEY_X1>, + <0x92 KEY_X2>, + <0xc0 KEY_END>, + <0xc1 KEY_GO_BEGINNING>, + <0x9d KEY_PLAYPAUSE>, + <0xc4 KEY_STOP>, + <0x94 KEY_EQUAL>, + <0x9e KEY_YELLOW>, + <0x9f KEY_BLUE>, + <0xcb KEY_APPLICATION>, + <0xc5 KEY_POS>; + }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi index 78ebdd048e74..9e19b61272ac 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -659,8 +659,10 @@ compatible = "operating-points-v2"; opp-shared; - nvmem-cells = <&cpul_leakage>, <&cpul_opp_info>, <&specification_serial_number>; - nvmem-cell-names = "leakage", "opp-info", "specification_serial_number"; + nvmem-cells = <&cpul_leakage>, <&cpul_opp_info>, + <&specification_serial_number>, <&customer_demand>; + nvmem-cell-names = "leakage", "opp-info", + "specification_serial_number", "customer_demand"; rockchip,supported-hw; rockchip,opp-shared-dsu; @@ -674,6 +676,18 @@ 1454 1475 5 1476 9999 6 >; + rockchip,pvtm-voltage-sel-B4 = < + 0 1330 0 + 1331 1365 1 + 1366 1390 2 + 1391 1410 3 + 1411 1434 4 + 1435 1458 5 + 1459 1482 6 + 1483 1506 7 + 1507 1530 8 + 1531 9999 9 + >; rockchip,pvtm-voltage-sel = < 0 1410 0 1411 1434 1 @@ -712,35 +726,35 @@ /* RK3588 cluster0 OPPs */ opp-408000000 { - opp-supported-hw = <0xf9 0xffff>; + opp-supported-hw = <0xe9 0xffff>; opp-hz = /bits/ 64 <408000000>; opp-microvolt = <675000 675000 950000>, <675000 675000 950000>; clock-latency-ns = <40000>; }; opp-600000000 { - opp-supported-hw = <0xf9 0xffff>; + opp-supported-hw = <0xe9 0xffff>; opp-hz = /bits/ 64 <600000000>; opp-microvolt = <675000 675000 950000>, <675000 675000 950000>; clock-latency-ns = <40000>; }; opp-816000000 { - opp-supported-hw = <0xf9 0xffff>; + opp-supported-hw = <0xe9 0xffff>; opp-hz = /bits/ 64 <816000000>; opp-microvolt = <675000 675000 950000>, <675000 675000 950000>; clock-latency-ns = <40000>; }; opp-1008000000 { - opp-supported-hw = <0xf9 0xffff>; + opp-supported-hw = <0xe9 0xffff>; opp-hz = /bits/ 64 <1008000000>; opp-microvolt = <675000 675000 950000>, <675000 675000 950000>; clock-latency-ns = <40000>; }; opp-1200000000 { - opp-supported-hw = <0xf9 0xffff>; + opp-supported-hw = <0xe9 0xffff>; opp-hz = /bits/ 64 <1200000000>; opp-microvolt = <712500 712500 950000>, <712500 712500 950000>; @@ -759,7 +773,7 @@ clock-latency-ns = <40000>; }; opp-1416000000 { - opp-supported-hw = <0xf9 0xffff>; + opp-supported-hw = <0xe9 0xffff>; opp-hz = /bits/ 64 <1416000000>; opp-microvolt = <762500 762500 950000>, <762500 762500 950000>; @@ -779,7 +793,7 @@ opp-suspend; }; opp-1608000000 { - opp-supported-hw = <0xf9 0xffff>; + opp-supported-hw = <0xe9 0xffff>; opp-hz = /bits/ 64 <1608000000>; opp-microvolt = <850000 850000 950000>, <850000 850000 950000>; @@ -798,7 +812,7 @@ clock-latency-ns = <40000>; }; opp-1800000000 { - opp-supported-hw = <0xf9 0xffff>; + opp-supported-hw = <0xe9 0xffff>; opp-hz = /bits/ 64 <1800000000>; opp-microvolt = <950000 950000 950000>, <950000 950000 950000>; @@ -817,6 +831,135 @@ clock-latency-ns = <40000>; }; + opp-b-408000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <675000 675000 950000>, + <675000 675000 950000>; + opp-microvolt-L0 = <712500 712500 950000>, + <712500 712500 950000>; + opp-microvolt-L1 = <700000 700000 950000>, + <700000 700000 950000>; + opp-microvolt-L2 = <687500 687500 950000>, + <687500 687500 950000>; + clock-latency-ns = <40000>; + }; + opp-b-600000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <675000 675000 950000>, + <675000 675000 950000>; + opp-microvolt-L0 = <712500 712500 950000>, + <712500 712500 950000>; + opp-microvolt-L1 = <700000 700000 950000>, + <700000 700000 950000>; + opp-microvolt-L2 = <687500 687500 950000>, + <687500 687500 950000>; + clock-latency-ns = <40000>; + }; + opp-b-816000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <675000 675000 950000>, + <675000 675000 950000>; + opp-microvolt-L0 = <712500 712500 950000>, + <712500 712500 950000>; + opp-microvolt-L1 = <700000 700000 950000>, + <700000 700000 950000>; + opp-microvolt-L2 = <687500 687500 950000>, + <687500 687500 950000>; + clock-latency-ns = <40000>; + }; + opp-b-1008000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <675000 675000 950000>, + <675000 675000 950000>; + opp-microvolt-L0 = <712500 712500 950000>, + <712500 712500 950000>; + opp-microvolt-L1 = <700000 700000 950000>, + <700000 700000 950000>; + opp-microvolt-L2 = <687500 687500 950000>, + <687500 687500 950000>; + clock-latency-ns = <40000>; + }; + opp-b-1200000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <750000 750000 950000>, + <750000 750000 950000>; + opp-microvolt-L1 = <737500 737500 950000>, + <737500 737500 950000>; + opp-microvolt-L2 = <725000 725000 950000>, + <725000 725000 950000>; + opp-microvolt-L3 = <712500 712500 950000>, + <712500 712500 950000>; + opp-microvolt-L4 = <700000 700000 950000>, + <700000 700000 950000>; + opp-microvolt-L5 = <700000 700000 950000>, + <700000 700000 950000>; + opp-microvolt-L6 = <687500 687500 950000>, + <687500 687500 950000>; + opp-microvolt-L7 = <675000 675000 950000>, + <675000 675000 950000>; + opp-microvolt-L8 = <675000 675000 950000>, + <675000 675000 950000>; + opp-microvolt-L9 = <675000 675000 950000>, + <675000 675000 950000>; + clock-latency-ns = <40000>; + }; + opp-b-1416000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <800000 800000 950000>, + <800000 800000 950000>; + opp-microvolt-L1 = <787500 787500 950000>, + <787500 787500 950000>; + opp-microvolt-L2 = <775000 775000 950000>, + <775000 775000 950000>; + opp-microvolt-L3 = <762500 762500 950000>, + <762500 762500 950000>; + opp-microvolt-L4 = <750000 750000 950000>, + <750000 750000 950000>; + opp-microvolt-L5 = <737500 737500 950000>, + <737500 737500 950000>; + opp-microvolt-L6 = <725000 725000 950000>, + <725000 725000 950000>; + opp-microvolt-L7 = <725000 725000 950000>, + <725000 725000 950000>; + opp-microvolt-L8 = <712500 712500 950000>, + <712500 712500 950000>; + opp-microvolt-L9 = <712500 712500 950000>, + <712500 712500 950000>; + clock-latency-ns = <40000>; + opp-suspend; + }; + opp-b-1608000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <887500 887500 950000>, + <887500 887500 950000>; + opp-microvolt-L1 = <875000 875000 950000>, + <875000 875000 950000>; + opp-microvolt-L2 = <862500 862500 950000>, + <862500 862500 950000>; + opp-microvolt-L3 = <850000 850000 950000>, + <850000 850000 950000>; + opp-microvolt-L4 = <837500 837500 950000>, + <837500 837500 950000>; + opp-microvolt-L5 = <825000 825000 950000>, + <825000 825000 950000>; + opp-microvolt-L6 = <812500 812500 950000>, + <812500 812500 950000>; + opp-microvolt-L7 = <800000 800000 950000>, + <800000 800000 950000>; + opp-microvolt-L8 = <800000 800000 950000>, + <800000 800000 950000>; + opp-microvolt-L9 = <787500 787500 950000>, + <787500 787500 950000>; + clock-latency-ns = <40000>; + }; + /* RK3588J/M cluster0 OPPs */ opp-j-m-408000000 { opp-supported-hw = <0x06 0xffff>; @@ -922,8 +1065,10 @@ compatible = "operating-points-v2"; opp-shared; - nvmem-cells = <&cpub0_leakage>, <&cpub01_opp_info>, <&specification_serial_number>; - nvmem-cell-names = "leakage", "opp-info", "specification_serial_number"; + nvmem-cells = <&cpub0_leakage>, <&cpub01_opp_info>, + <&specification_serial_number>, <&customer_demand>; + nvmem-cell-names = "leakage", "opp-info", + "specification_serial_number", "customer_demand"; rockchip,supported-hw; rockchip,pvtm-hw = <0x06>; @@ -937,6 +1082,19 @@ 1675 1704 6 1705 9999 7 >; + rockchip,pvtm-voltage-sel-B4 = < + 0 1525 0 + 1526 1545 1 + 1546 1565 2 + 1566 1595 3 + 1596 1615 4 + 1616 1640 5 + 1641 1675 6 + 1676 1710 7 + 1711 1743 8 + 1744 1776 9 + 1777 9999 10 + >; rockchip,pvtm-voltage-sel = < 0 1595 0 1596 1615 1 @@ -977,7 +1135,7 @@ /* RK3588 cluster1 OPPs */ opp-408000000 { - opp-supported-hw = <0xf9 0xffff>; + opp-supported-hw = <0xe9 0xffff>; opp-hz = /bits/ 64 <408000000>; opp-microvolt = <675000 675000 1000000>, <675000 675000 1000000>; @@ -985,35 +1143,35 @@ opp-suspend; }; opp-600000000 { - opp-supported-hw = <0xf9 0xffff>; + opp-supported-hw = <0xe9 0xffff>; opp-hz = /bits/ 64 <600000000>; opp-microvolt = <675000 675000 1000000>, <675000 675000 1000000>; clock-latency-ns = <40000>; }; opp-816000000 { - opp-supported-hw = <0xf9 0xffff>; + opp-supported-hw = <0xe9 0xffff>; opp-hz = /bits/ 64 <816000000>; opp-microvolt = <675000 675000 1000000>, <675000 675000 1000000>; clock-latency-ns = <40000>; }; opp-1008000000 { - opp-supported-hw = <0xf9 0xffff>; + opp-supported-hw = <0xe9 0xffff>; opp-hz = /bits/ 64 <1008000000>; opp-microvolt = <675000 675000 1000000>, <675000 675000 1000000>; clock-latency-ns = <40000>; }; opp-1200000000 { - opp-supported-hw = <0xf9 0xffff>; + opp-supported-hw = <0xe9 0xffff>; opp-hz = /bits/ 64 <1200000000>; opp-microvolt = <675000 675000 1000000>, <675000 675000 1000000>; clock-latency-ns = <40000>; }; opp-1416000000 { - opp-supported-hw = <0xf9 0xffff>; + opp-supported-hw = <0xe9 0xffff>; opp-hz = /bits/ 64 <1416000000>; opp-microvolt = <725000 725000 1000000>, <725000 725000 1000000>; @@ -1032,7 +1190,7 @@ clock-latency-ns = <40000>; }; opp-1608000000 { - opp-supported-hw = <0xf9 0xffff>; + opp-supported-hw = <0xe9 0xffff>; opp-hz = /bits/ 64 <1608000000>; opp-microvolt = <762500 762500 1000000>, <762500 762500 1000000>; @@ -1051,7 +1209,7 @@ clock-latency-ns = <40000>; }; opp-1800000000 { - opp-supported-hw = <0xf9 0xffff>; + opp-supported-hw = <0xe9 0xffff>; opp-hz = /bits/ 64 <1800000000>; opp-microvolt = <850000 850000 1000000>, <850000 850000 1000000>; @@ -1072,7 +1230,7 @@ clock-latency-ns = <40000>; }; opp-2016000000 { - opp-supported-hw = <0xf9 0xffff>; + opp-supported-hw = <0xe9 0xffff>; opp-hz = /bits/ 64 <2016000000>; opp-microvolt = <925000 925000 1000000>, <925000 925000 1000000>; @@ -1093,7 +1251,7 @@ clock-latency-ns = <40000>; }; opp-2208000000 { - opp-supported-hw = <0xf9 0xffff>; + opp-supported-hw = <0xe9 0xffff>; opp-hz = /bits/ 64 <2208000000>; opp-microvolt = <987500 987500 1000000>, <987500 987500 1000000>; @@ -1114,34 +1272,209 @@ clock-latency-ns = <40000>; }; opp-2256000000 { - opp-supported-hw = <0xf9 0x13>; + opp-supported-hw = <0xe9 0x13>; opp-hz = /bits/ 64 <2256000000>; opp-microvolt = <1000000 1000000 1000000>, <1000000 1000000 1000000>; clock-latency-ns = <40000>; }; opp-2304000000 { - opp-supported-hw = <0xf9 0x24>; + opp-supported-hw = <0xe9 0x24>; opp-hz = /bits/ 64 <2304000000>; opp-microvolt = <1000000 1000000 1000000>, <1000000 1000000 1000000>; clock-latency-ns = <40000>; }; opp-2352000000 { - opp-supported-hw = <0xf9 0x48>; + opp-supported-hw = <0xe9 0x48>; opp-hz = /bits/ 64 <2352000000>; opp-microvolt = <1000000 1000000 1000000>, <1000000 1000000 1000000>; clock-latency-ns = <40000>; }; opp-2400000000 { - opp-supported-hw = <0xf9 0x80>; + opp-supported-hw = <0xe9 0x80>; opp-hz = /bits/ 64 <2400000000>; opp-microvolt = <1000000 1000000 1000000>, <1000000 1000000 1000000>; clock-latency-ns = <40000>; }; + opp-b-408000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <675000 675000 950000>, + <675000 675000 950000>; + opp-microvolt-L0 = <712500 712500 950000>, + <712500 712500 950000>; + opp-microvolt-L1 = <700000 700000 950000>, + <700000 700000 950000>; + opp-microvolt-L2 = <687500 687500 950000>, + <687500 687500 950000>; + clock-latency-ns = <40000>; + opp-suspend; + }; + opp-b-600000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <675000 675000 950000>, + <675000 675000 950000>; + opp-microvolt-L0 = <712500 712500 950000>, + <712500 712500 950000>; + opp-microvolt-L1 = <700000 700000 950000>, + <700000 700000 950000>; + opp-microvolt-L2 = <687500 687500 950000>, + <687500 687500 950000>; + clock-latency-ns = <40000>; + }; + opp-b-816000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <675000 675000 950000>, + <675000 675000 950000>; + opp-microvolt-L0 = <712500 712500 950000>, + <712500 712500 950000>; + opp-microvolt-L1 = <700000 700000 950000>, + <700000 700000 950000>; + opp-microvolt-L2 = <687500 687500 950000>, + <687500 687500 950000>; + clock-latency-ns = <40000>; + }; + opp-b-1008000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <675000 675000 950000>, + <675000 675000 950000>; + opp-microvolt-L0 = <712500 712500 950000>, + <712500 712500 950000>; + opp-microvolt-L1 = <700000 700000 950000>, + <700000 700000 950000>; + opp-microvolt-L2 = <687500 687500 950000>, + <687500 687500 950000>; + clock-latency-ns = <40000>; + }; + opp-b-1200000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <675000 675000 950000>, + <675000 675000 950000>; + opp-microvolt-L0 = <712500 712500 950000>, + <712500 712500 950000>; + opp-microvolt-L1 = <700000 700000 950000>, + <700000 700000 950000>; + opp-microvolt-L2 = <687500 687500 950000>, + <687500 687500 950000>; + clock-latency-ns = <40000>; + }; + opp-b-1416000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <750000 750000 1000000>, + <750000 750000 1000000>; + opp-microvolt-L1 = <737500 737500 1000000>, + <737500 737500 1000000>; + opp-microvolt-L2 = <737500 737500 1000000>, + <737500 737500 1000000>; + opp-microvolt-L3 = <725000 725000 1000000>, + <725000 725000 1000000>; + opp-microvolt-L4 = <725000 725000 1000000>, + <725000 725000 1000000>; + opp-microvolt-L5 = <712500 712500 1000000>, + <712500 712500 1000000>; + opp-microvolt-L6 = <700000 700000 1000000>, + <700000 700000 1000000>; + opp-microvolt-L7 = <700000 700000 1000000>, + <700000 700000 1000000>; + opp-microvolt-L8 = <687500 687500 1000000>, + <687500 687500 1000000>; + opp-microvolt-L9 = <675000 675000 1000000>, + <675000 675000 1000000>; + opp-microvolt-L10 = <675000 675000 1000000>, + <675000 675000 1000000>; + clock-latency-ns = <40000>; + }; + opp-b-1608000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <800000 800000 1000000>, + <800000 800000 1000000>; + opp-microvolt-L1 = <787500 787500 1000000>, + <787500 787500 1000000>; + opp-microvolt-L2 = <775000 775000 1000000>, + <775000 775000 1000000>; + opp-microvolt-L3 = <762500 762500 1000000>, + <762500 762500 1000000>; + opp-microvolt-L4 = <762500 762500 1000000>, + <762500 762500 1000000>; + opp-microvolt-L5 = <750000 750000 1000000>, + <750000 750000 1000000>; + opp-microvolt-L6 = <737500 737500 1000000>, + <737500 737500 1000000>; + opp-microvolt-L7 = <725000 725000 1000000>, + <725000 725000 1000000>; + opp-microvolt-L8 = <712500 712500 1000000>, + <712500 712500 1000000>; + opp-microvolt-L9 = <700000 700000 1000000>, + <700000 700000 1000000>; + opp-microvolt-L10 = <700000 700000 1000000>, + <700000 700000 1000000>; + clock-latency-ns = <40000>; + }; + opp-b-1800000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <875000 875000 1000000>, + <875000 875000 1000000>; + opp-microvolt-L1 = <875000 875000 1000000>, + <875000 875000 1000000>; + opp-microvolt-L2 = <862500 862500 1000000>, + <862500 862500 1000000>; + opp-microvolt-L3 = <850000 850000 1000000>, + <850000 850000 1000000>; + opp-microvolt-L4 = <837500 837500 1000000>, + <837500 837500 1000000>; + opp-microvolt-L5 = <825000 825000 1000000>, + <825000 825000 1000000>; + opp-microvolt-L6 = <812500 812500 1000000>, + <812500 812500 1000000>; + opp-microvolt-L7 = <800000 800000 1000000>, + <800000 800000 1000000>; + opp-microvolt-L8 = <787500 787500 1000000>, + <787500 787500 1000000>; + opp-microvolt-L9 = <775000 775000 1000000>, + <775000 775000 1000000>; + opp-microvolt-L10 = <762500 762500 1000000>, + <762500 762500 1000000>; + clock-latency-ns = <40000>; + }; + opp-b-2016000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = /bits/ 64 <2016000000>; + opp-microvolt = <962500 962500 1000000>, + <962500 962500 1000000>; + opp-microvolt-L1 = <950000 950000 1000000>, + <950000 950000 1000000>; + opp-microvolt-L2 = <937500 937500 1000000>, + <937500 937500 1000000>; + opp-microvolt-L3 = <925000 925000 1000000>, + <925000 925000 1000000>; + opp-microvolt-L4 = <912500 912500 1000000>, + <912500 912500 1000000>; + opp-microvolt-L5 = <900000 900000 1000000>, + <900000 900000 1000000>; + opp-microvolt-L6 = <887500 887500 1000000>, + <887500 887500 1000000>; + opp-microvolt-L7 = <875000 875000 1000000>, + <875000 875000 1000000>; + opp-microvolt-L8 = <862500 862500 1000000>, + <862500 862500 1000000>; + opp-microvolt-L9 = <850000 850000 1000000>, + <850000 850000 1000000>; + opp-microvolt-L10 = <837500 837500 1000000>, + <837500 837500 1000000>; + clock-latency-ns = <40000>; + }; + /* RK3588J/M cluster1 OPPs */ opp-j-m-408000000 { opp-supported-hw = <0x06 0xffff>; @@ -1255,8 +1588,10 @@ compatible = "operating-points-v2"; opp-shared; - nvmem-cells = <&cpub1_leakage>, <&cpub23_opp_info>, <&specification_serial_number>; - nvmem-cell-names = "leakage", "opp-info", "specification_serial_number"; + nvmem-cells = <&cpub1_leakage>, <&cpub23_opp_info>, + <&specification_serial_number>, <&customer_demand>; + nvmem-cell-names = "leakage", "opp-info", + "specification_serial_number", "customer_demand"; rockchip,supported-hw; rockchip,pvtm-hw = <0x06>; @@ -1270,6 +1605,19 @@ 1675 1704 6 1705 9999 7 >; + rockchip,pvtm-voltage-sel-B4 = < + 0 1525 0 + 1526 1545 1 + 1546 1565 2 + 1566 1595 3 + 1596 1615 4 + 1616 1640 5 + 1641 1675 6 + 1676 1710 7 + 1711 1743 8 + 1744 1776 9 + 1777 9999 10 + >; rockchip,pvtm-voltage-sel = < 0 1595 0 1596 1615 1 @@ -1310,7 +1658,7 @@ /* RK3588 cluster2 OPPs */ opp-408000000 { - opp-supported-hw = <0xf9 0x0ffff>; + opp-supported-hw = <0xe9 0x0ffff>; opp-hz = /bits/ 64 <408000000>; opp-microvolt = <675000 675000 1000000>, <675000 675000 1000000>; @@ -1318,35 +1666,35 @@ opp-suspend; }; opp-600000000 { - opp-supported-hw = <0xf9 0xffff>; + opp-supported-hw = <0xe9 0xffff>; opp-hz = /bits/ 64 <600000000>; opp-microvolt = <675000 675000 1000000>, <675000 675000 1000000>; clock-latency-ns = <40000>; }; opp-816000000 { - opp-supported-hw = <0xf9 0xffff>; + opp-supported-hw = <0xe9 0xffff>; opp-hz = /bits/ 64 <816000000>; opp-microvolt = <675000 675000 1000000>, <675000 675000 1000000>; clock-latency-ns = <40000>; }; opp-1008000000 { - opp-supported-hw = <0xf9 0xffff>; + opp-supported-hw = <0xe9 0xffff>; opp-hz = /bits/ 64 <1008000000>; opp-microvolt = <675000 675000 1000000>, <675000 675000 1000000>; clock-latency-ns = <40000>; }; opp-1200000000 { - opp-supported-hw = <0xf9 0xffff>; + opp-supported-hw = <0xe9 0xffff>; opp-hz = /bits/ 64 <1200000000>; opp-microvolt = <675000 675000 1000000>, <675000 675000 1000000>; clock-latency-ns = <40000>; }; opp-1416000000 { - opp-supported-hw = <0xf9 0xffff>; + opp-supported-hw = <0xe9 0xffff>; opp-hz = /bits/ 64 <1416000000>; opp-microvolt = <725000 725000 1000000>, <725000 725000 1000000>; @@ -1365,7 +1713,7 @@ clock-latency-ns = <40000>; }; opp-1608000000 { - opp-supported-hw = <0xf9 0xffff>; + opp-supported-hw = <0xe9 0xffff>; opp-hz = /bits/ 64 <1608000000>; opp-microvolt = <762500 762500 1000000>, <762500 762500 1000000>; @@ -1384,7 +1732,7 @@ clock-latency-ns = <40000>; }; opp-1800000000 { - opp-supported-hw = <0xf9 0xffff>; + opp-supported-hw = <0xe9 0xffff>; opp-hz = /bits/ 64 <1800000000>; opp-microvolt = <850000 850000 1000000>, <850000 850000 1000000>; @@ -1405,7 +1753,7 @@ clock-latency-ns = <40000>; }; opp-2016000000 { - opp-supported-hw = <0xf9 0xffff>; + opp-supported-hw = <0xe9 0xffff>; opp-hz = /bits/ 64 <2016000000>; opp-microvolt = <925000 925000 1000000>, <925000 925000 1000000>; @@ -1426,7 +1774,7 @@ clock-latency-ns = <40000>; }; opp-2208000000 { - opp-supported-hw = <0xf9 0xffff>; + opp-supported-hw = <0xe9 0xffff>; opp-hz = /bits/ 64 <2208000000>; opp-microvolt = <987500 987500 1000000>, <987500 987500 1000000>; @@ -1443,34 +1791,209 @@ clock-latency-ns = <40000>; }; opp-2256000000 { - opp-supported-hw = <0xf9 0x13>; + opp-supported-hw = <0xe9 0x13>; opp-hz = /bits/ 64 <2256000000>; opp-microvolt = <1000000 1000000 1000000>, <1000000 1000000 1000000>; clock-latency-ns = <40000>; }; opp-2304000000 { - opp-supported-hw = <0xf9 0x24>; + opp-supported-hw = <0xe9 0x24>; opp-hz = /bits/ 64 <2304000000>; opp-microvolt = <1000000 1000000 1000000>, <1000000 1000000 1000000>; clock-latency-ns = <40000>; }; opp-2352000000 { - opp-supported-hw = <0xf9 0x48>; + opp-supported-hw = <0xe9 0x48>; opp-hz = /bits/ 64 <2352000000>; opp-microvolt = <1000000 1000000 1000000>, <1000000 1000000 1000000>; clock-latency-ns = <40000>; }; opp-2400000000 { - opp-supported-hw = <0xf9 0x80>; + opp-supported-hw = <0xe9 0x80>; opp-hz = /bits/ 64 <2400000000>; opp-microvolt = <1000000 1000000 1000000>, <1000000 1000000 1000000>; clock-latency-ns = <40000>; }; + opp-b-408000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <675000 675000 950000>, + <675000 675000 950000>; + opp-microvolt-L0 = <712500 712500 950000>, + <712500 712500 950000>; + opp-microvolt-L1 = <700000 700000 950000>, + <700000 700000 950000>; + opp-microvolt-L2 = <687500 687500 950000>, + <687500 687500 950000>; + clock-latency-ns = <40000>; + opp-suspend; + }; + opp-b-600000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <675000 675000 950000>, + <675000 675000 950000>; + opp-microvolt-L0 = <712500 712500 950000>, + <712500 712500 950000>; + opp-microvolt-L1 = <700000 700000 950000>, + <700000 700000 950000>; + opp-microvolt-L2 = <687500 687500 950000>, + <687500 687500 950000>; + clock-latency-ns = <40000>; + }; + opp-b-816000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <675000 675000 950000>, + <675000 675000 950000>; + opp-microvolt-L0 = <712500 712500 950000>, + <712500 712500 950000>; + opp-microvolt-L1 = <700000 700000 950000>, + <700000 700000 950000>; + opp-microvolt-L2 = <687500 687500 950000>, + <687500 687500 950000>; + clock-latency-ns = <40000>; + }; + opp-b-1008000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <675000 675000 950000>, + <675000 675000 950000>; + opp-microvolt-L0 = <712500 712500 950000>, + <712500 712500 950000>; + opp-microvolt-L1 = <700000 700000 950000>, + <700000 700000 950000>; + opp-microvolt-L2 = <687500 687500 950000>, + <687500 687500 950000>; + clock-latency-ns = <40000>; + }; + opp-b-1200000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <675000 675000 950000>, + <675000 675000 950000>; + opp-microvolt-L0 = <712500 712500 950000>, + <712500 712500 950000>; + opp-microvolt-L1 = <700000 700000 950000>, + <700000 700000 950000>; + opp-microvolt-L2 = <687500 687500 950000>, + <687500 687500 950000>; + clock-latency-ns = <40000>; + }; + opp-b-1416000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <750000 750000 1000000>, + <750000 750000 1000000>; + opp-microvolt-L1 = <737500 737500 1000000>, + <737500 737500 1000000>; + opp-microvolt-L2 = <737500 737500 1000000>, + <737500 737500 1000000>; + opp-microvolt-L3 = <725000 725000 1000000>, + <725000 725000 1000000>; + opp-microvolt-L4 = <725000 725000 1000000>, + <725000 725000 1000000>; + opp-microvolt-L5 = <712500 712500 1000000>, + <712500 712500 1000000>; + opp-microvolt-L6 = <700000 700000 1000000>, + <700000 700000 1000000>; + opp-microvolt-L7 = <700000 700000 1000000>, + <700000 700000 1000000>; + opp-microvolt-L8 = <687500 687500 1000000>, + <687500 687500 1000000>; + opp-microvolt-L9 = <675000 675000 1000000>, + <675000 675000 1000000>; + opp-microvolt-L10 = <675000 675000 1000000>, + <675000 675000 1000000>; + clock-latency-ns = <40000>; + }; + opp-b-1608000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <800000 800000 1000000>, + <800000 800000 1000000>; + opp-microvolt-L1 = <787500 787500 1000000>, + <787500 787500 1000000>; + opp-microvolt-L2 = <775000 775000 1000000>, + <775000 775000 1000000>; + opp-microvolt-L3 = <762500 762500 1000000>, + <762500 762500 1000000>; + opp-microvolt-L4 = <762500 762500 1000000>, + <762500 762500 1000000>; + opp-microvolt-L5 = <750000 750000 1000000>, + <750000 750000 1000000>; + opp-microvolt-L6 = <737500 737500 1000000>, + <737500 737500 1000000>; + opp-microvolt-L7 = <725000 725000 1000000>, + <725000 725000 1000000>; + opp-microvolt-L8 = <712500 712500 1000000>, + <712500 712500 1000000>; + opp-microvolt-L9 = <700000 700000 1000000>, + <700000 700000 1000000>; + opp-microvolt-L10 = <700000 700000 1000000>, + <700000 700000 1000000>; + clock-latency-ns = <40000>; + }; + opp-b-1800000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <875000 875000 1000000>, + <875000 875000 1000000>; + opp-microvolt-L1 = <875000 875000 1000000>, + <875000 875000 1000000>; + opp-microvolt-L2 = <862500 862500 1000000>, + <862500 862500 1000000>; + opp-microvolt-L3 = <850000 850000 1000000>, + <850000 850000 1000000>; + opp-microvolt-L4 = <837500 837500 1000000>, + <837500 837500 1000000>; + opp-microvolt-L5 = <825000 825000 1000000>, + <825000 825000 1000000>; + opp-microvolt-L6 = <812500 812500 1000000>, + <812500 812500 1000000>; + opp-microvolt-L7 = <800000 800000 1000000>, + <800000 800000 1000000>; + opp-microvolt-L8 = <787500 787500 1000000>, + <787500 787500 1000000>; + opp-microvolt-L9 = <775000 775000 1000000>, + <775000 775000 1000000>; + opp-microvolt-L10 = <762500 762500 1000000>, + <762500 762500 1000000>; + clock-latency-ns = <40000>; + }; + opp-b-2016000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = /bits/ 64 <2016000000>; + opp-microvolt = <962500 962500 1000000>, + <962500 962500 1000000>; + opp-microvolt-L1 = <950000 950000 1000000>, + <950000 950000 1000000>; + opp-microvolt-L2 = <937500 937500 1000000>, + <937500 937500 1000000>; + opp-microvolt-L3 = <925000 925000 1000000>, + <925000 925000 1000000>; + opp-microvolt-L4 = <912500 912500 1000000>, + <912500 912500 1000000>; + opp-microvolt-L5 = <900000 900000 1000000>, + <900000 900000 1000000>; + opp-microvolt-L6 = <887500 887500 1000000>, + <887500 887500 1000000>; + opp-microvolt-L7 = <875000 875000 1000000>, + <875000 875000 1000000>; + opp-microvolt-L8 = <862500 862500 1000000>, + <862500 862500 1000000>; + opp-microvolt-L9 = <850000 850000 1000000>, + <850000 850000 1000000>; + opp-microvolt-L10 = <837500 837500 1000000>, + <837500 837500 1000000>; + clock-latency-ns = <40000>; + }; + /* RK3588J/M cluster2 OPPs */ opp-j-m-408000000 { opp-supported-hw = <0x06 0xffff>; @@ -1758,8 +2281,10 @@ dmc_opp_table: dmc-opp-table { compatible = "operating-points-v2"; - nvmem-cells = <&log_leakage>, <&dmc_opp_info>, <&specification_serial_number>; - nvmem-cell-names = "leakage", "opp-info", "specification_serial_number"; + nvmem-cells = <&log_leakage>, <&dmc_opp_info>, + <&specification_serial_number>, <&customer_demand>; + nvmem-cell-names = "leakage", "opp-info", + "specification_serial_number", "customer_demand"; rockchip,supported-hw; rockchip,leakage-voltage-sel = < @@ -1810,7 +2335,7 @@ <700000 700000 800000>; }; opp-2750000000 { - opp-supported-hw = <0xf9 0xffff>; + opp-supported-hw = <0xe9 0xffff>; opp-hz = /bits/ 64 <2750000000>; opp-microvolt = <875000 875000 875000>, <750000 750000 800000>; @@ -1822,6 +2347,18 @@ <700000 700000 800000>; }; + opp-b-1848000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = /bits/ 64 <1848000000>; + opp-microvolt = <875000 875000 875000>, + <750000 750000 750000>; + opp-microvolt-L1 = <850000 850000 875000>, + <750000 750000 750000>; + opp-microvolt-L2 = <837500 837500 875000>, + <725000 725000 750000>; + opp-microvolt-L3 = <825000 820000 875000>, + <700000 700000 750000>; + }; /* RK3588J/M dmc OPPs */ opp-j-m-528000000 { opp-supported-hw = <0x06 0xffff>; @@ -2390,8 +2927,10 @@ gpu_opp_table: gpu-opp-table { compatible = "operating-points-v2"; - nvmem-cells = <&gpu_leakage>, <&gpu_opp_info>, <&specification_serial_number>; - nvmem-cell-names = "leakage", "opp-info", "specification_serial_number"; + nvmem-cells = <&gpu_leakage>, <&gpu_opp_info>, + <&specification_serial_number>, <&customer_demand>; + nvmem-cell-names = "leakage", "opp-info", + "specification_serial_number", "customer_demand"; rockchip,supported-hw; rockchip,pvtm-hw = <0x04>; @@ -2403,6 +2942,17 @@ 870 894 4 895 9999 5 >; + rockchip,pvtm-voltage-sel-B4 = < + 0 755 0 + 756 775 1 + 776 795 2 + 796 815 3 + 816 835 4 + 836 860 5 + 861 885 6 + 886 910 7 + 911 9999 8 + >; rockchip,pvtm-voltage-sel = < 0 815 0 816 835 1 @@ -2439,31 +2989,31 @@ /* RK3588 gpu OPPs */ opp-300000000 { - opp-supported-hw = <0xf9 0xffff>; + opp-supported-hw = <0xe9 0xffff>; opp-hz = /bits/ 64 <300000000>; opp-microvolt = <675000 675000 850000>, <675000 675000 850000>; }; opp-400000000 { - opp-supported-hw = <0xf9 0xffff>; + opp-supported-hw = <0xe9 0xffff>; opp-hz = /bits/ 64 <400000000>; opp-microvolt = <675000 675000 850000>, <675000 675000 850000>; }; opp-500000000 { - opp-supported-hw = <0xf9 0xffff>; + opp-supported-hw = <0xe9 0xffff>; opp-hz = /bits/ 64 <500000000>; opp-microvolt = <675000 675000 850000>, <675000 675000 850000>; }; opp-600000000 { - opp-supported-hw = <0xf9 0xffff>; + opp-supported-hw = <0xe9 0xffff>; opp-hz = /bits/ 64 <600000000>; opp-microvolt = <675000 675000 850000>, <675000 675000 850000>; }; opp-700000000 { - opp-supported-hw = <0xf9 0xffff>; + opp-supported-hw = <0xe9 0xffff>; opp-hz = /bits/ 64 <700000000>; opp-microvolt = <700000 700000 850000>, <700000 700000 850000>; @@ -2477,7 +3027,7 @@ <675000 675000 850000>; }; opp-800000000 { - opp-supported-hw = <0xf9 0xffff>; + opp-supported-hw = <0xe9 0xffff>; opp-hz = /bits/ 64 <800000000>; opp-microvolt = <750000 750000 850000>, <750000 750000 850000>; @@ -2493,7 +3043,7 @@ <700000 700000 850000>; }; opp-900000000 { - opp-supported-hw = <0xf9 0xffff>; + opp-supported-hw = <0xe9 0xffff>; opp-hz = /bits/ 64 <900000000>; opp-microvolt = <800000 800000 850000>, <800000 800000 850000>; @@ -2509,7 +3059,7 @@ <737500 737500 850000>; }; opp-1000000000 { - opp-supported-hw = <0xf9 0xffff>; + opp-supported-hw = <0xe9 0xffff>; opp-hz = /bits/ 64 <1000000000>; opp-microvolt = <850000 850000 850000>, <850000 850000 850000>; @@ -2525,6 +3075,119 @@ <787500 787500 850000>; }; + opp-b-300000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <675000 675000 850000>, + <675000 675000 850000>; + opp-microvolt-L0 = <712500 712500 850000>, + <712500 712500 850000>; + opp-microvolt-L1 = <700000 700000 850000>, + <700000 700000 850000>; + opp-microvolt-L2 = <687500 687500 850000>, + <687500 687500 850000>; + }; + opp-b-400000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <675000 675000 850000>, + <675000 675000 850000>; + opp-microvolt-L0 = <712500 712500 850000>, + <712500 712500 850000>; + opp-microvolt-L1 = <700000 700000 850000>, + <700000 700000 850000>; + opp-microvolt-L2 = <687500 687500 850000>, + <687500 687500 850000>; + }; + opp-b-500000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <675000 675000 850000>, + <675000 675000 850000>; + opp-microvolt-L0 = <712500 712500 850000>, + <712500 712500 850000>; + opp-microvolt-L1 = <700000 700000 850000>, + <700000 700000 850000>; + opp-microvolt-L2 = <687500 687500 850000>, + <687500 687500 850000>; + }; + opp-b-600000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <675000 675000 850000>, + <675000 675000 850000>; + opp-microvolt-L0 = <712500 712500 850000>, + <712500 712500 850000>; + opp-microvolt-L1 = <700000 700000 850000>, + <700000 700000 850000>; + opp-microvolt-L2 = <687500 687500 850000>, + <687500 687500 850000>; + }; + opp-b-700000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = /bits/ 64 <700000000>; + opp-microvolt-L0 = <737500 737500 850000>, + <737500 737500 850000>; + opp-microvolt-L1 = <725000 725000 850000>, + <725000 725000 850000>; + opp-microvolt-L2 = <712500 712500 850000>, + <712500 712500 850000>; + opp-microvolt-L3 = <700000 700000 850000>, + <700000 700000 850000>; + opp-microvolt-L4 = <700000 700000 850000>, + <700000 700000 850000>; + opp-microvolt-L5 = <687500 687500 850000>, + <687500 687500 850000>; + opp-microvolt-L6 = <675000 675000 850000>, + <675000 675000 850000>; + opp-microvolt-L7 = <675000 675000 850000>, + <675000 675000 850000>; + opp-microvolt-L8 = <675000 675000 850000>, + <675000 675000 850000>; + }; + opp-b-800000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = /bits/ 64 <800000000>; + opp-microvolt-L0 = <787500 787500 850000>, + <787500 787500 850000>; + opp-microvolt-L1 = <775000 775000 850000>, + <775000 775000 850000>; + opp-microvolt-L2 = <762500 762500 850000>, + <762500 762500 850000>; + opp-microvolt-L3 = <750000 750000 850000>, + <750000 750000 850000>; + opp-microvolt-L4 = <737500 737500 850000>, + <737500 737500 850000>; + opp-microvolt-L5 = <725000 725000 850000>, + <725000 725000 850000>; + opp-microvolt-L6 = <712500 712500 850000>, + <712500 712500 850000>; + opp-microvolt-L7 = <700000 700000 850000>, + <700000 700000 850000>; + opp-microvolt-L8 = <700000 700000 850000>, + <700000 700000 850000>; + }; + opp-b-950000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = /bits/ 64 <950000000>; + opp-microvolt = <850000 850000 850000>, + <850000 850000 850000>; + opp-microvolt-L2 = <837500 837500 850000>, + <837500 837500 850000>; + opp-microvolt-L3 = <825000 825000 850000>, + <825000 825000 850000>; + opp-microvolt-L4 = <812500 812500 850000>, + <812500 812500 850000>; + opp-microvolt-L5 = <800000 800000 850000>, + <800000 800000 850000>; + opp-microvolt-L6 = <787500 787500 850000>, + <787500 787500 850000>; + opp-microvolt-L7 = <775000 775000 850000>, + <775000 775000 850000>; + opp-microvolt-L8 = <762500 762500 850000>, + <762500 762500 850000>; + }; + /* RK3588J/M gpu OPPs */ opp-j-m-300000000 { opp-supported-hw = <0x06 0xffff>; @@ -3484,8 +4147,10 @@ npu_opp_table: npu-opp-table { compatible = "operating-points-v2"; - nvmem-cells = <&npu_leakage>, <&npu_opp_info>, <&specification_serial_number>; - nvmem-cell-names = "leakage", "opp-info", "specification_serial_number"; + nvmem-cells = <&npu_leakage>, <&npu_opp_info>, + <&specification_serial_number>, <&customer_demand>; + nvmem-cell-names = "leakage", "opp-info", + "specification_serial_number", "customer_demand"; rockchip,supported-hw; rockchip,pvtm-hw = <0x06>; @@ -3497,6 +4162,17 @@ 870 894 4 895 9999 5 >; + rockchip,pvtm-voltage-sel-B4 = < + 0 755 0 + 756 775 1 + 776 795 2 + 796 815 3 + 816 835 4 + 836 860 5 + 861 885 6 + 886 910 7 + 911 9999 8 + >; rockchip,pvtm-voltage-sel = < 0 815 0 816 835 1 @@ -3534,7 +4210,7 @@ /* RK3588 npu OPPs */ opp-300000000 { - opp-supported-hw = <0xf9 0xffff>; + opp-supported-hw = <0xe9 0xffff>; opp-hz = /bits/ 64 <300000000>; opp-microvolt = <700000 700000 850000>, <700000 700000 850000>; @@ -3550,7 +4226,7 @@ <675000 675000 850000>; }; opp-400000000 { - opp-supported-hw = <0xf9 0xffff>; + opp-supported-hw = <0xe9 0xffff>; opp-hz = /bits/ 64 <400000000>; opp-microvolt = <700000 700000 850000>, <700000 700000 850000>; @@ -3566,7 +4242,7 @@ <675000 675000 850000>; }; opp-500000000 { - opp-supported-hw = <0xf9 0xffff>; + opp-supported-hw = <0xe9 0xffff>; opp-hz = /bits/ 64 <500000000>; opp-microvolt = <700000 700000 850000>, <700000 700000 850000>; @@ -3582,7 +4258,7 @@ <675000 675000 850000>; }; opp-600000000 { - opp-supported-hw = <0xf9 0xffff>; + opp-supported-hw = <0xe9 0xffff>; opp-hz = /bits/ 64 <600000000>; opp-microvolt = <700000 700000 850000>, <700000 700000 850000>; @@ -3598,7 +4274,7 @@ <675000 675000 850000>; }; opp-700000000 { - opp-supported-hw = <0xf9 0xffff>; + opp-supported-hw = <0xe9 0xffff>; opp-hz = /bits/ 64 <700000000>; opp-microvolt = <700000 700000 850000>, <700000 700000 850000>; @@ -3610,7 +4286,7 @@ <675000 675000 850000>; }; opp-800000000 { - opp-supported-hw = <0xf9 0xffff>; + opp-supported-hw = <0xe9 0xffff>; opp-hz = /bits/ 64 <800000000>; opp-microvolt = <750000 750000 850000>, <750000 750000 850000>; @@ -3624,7 +4300,7 @@ <700000 700000 850000>; }; opp-900000000 { - opp-supported-hw = <0xf9 0xffff>; + opp-supported-hw = <0xe9 0xffff>; opp-hz = /bits/ 64 <900000000>; opp-microvolt = <800000 800000 850000>, <800000 800000 850000>; @@ -3640,7 +4316,7 @@ <737500 737500 850000>; }; opp-1000000000 { - opp-supported-hw = <0xf9 0xffff>; + opp-supported-hw = <0xe9 0xffff>; opp-hz = /bits/ 64 <1000000000>; opp-microvolt = <850000 850000 850000>, <850000 850000 850000>; @@ -3656,6 +4332,135 @@ <787500 787500 850000>; }; + opp-b-300000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <675000 675000 850000>, + <675000 675000 850000>; + opp-microvolt-L0 = <725000 725000 850000>, + <725000 725000 850000>; + opp-microvolt-L1 = <712500 712500 850000>, + <712500 712500 850000>; + opp-microvolt-L2 = <712500 712500 850000>, + <712500 712500 850000>; + opp-microvolt-L3 = <700000 700000 850000>, + <700000 700000 850000>; + opp-microvolt-L4 = <687500 687500 850000>, + <687500 687500 850000>; + }; + opp-b-400000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <675000 675000 850000>, + <675000 675000 850000>; + opp-microvolt-L0 = <725000 725000 850000>, + <725000 725000 850000>; + opp-microvolt-L1 = <712500 712500 850000>, + <712500 712500 850000>; + opp-microvolt-L2 = <712500 712500 850000>, + <712500 712500 850000>; + opp-microvolt-L3 = <700000 700000 850000>, + <700000 700000 850000>; + opp-microvolt-L4 = <687500 687500 850000>, + <687500 687500 850000>; + }; + opp-b-500000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <675000 675000 850000>, + <675000 675000 850000>; + opp-microvolt-L0 = <725000 725000 850000>, + <725000 725000 850000>; + opp-microvolt-L1 = <712500 712500 850000>, + <712500 712500 850000>; + opp-microvolt-L2 = <712500 712500 850000>, + <712500 712500 850000>; + opp-microvolt-L3 = <700000 700000 850000>, + <700000 700000 850000>; + opp-microvolt-L4 = <687500 687500 850000>, + <687500 687500 850000>; + }; + opp-b-600000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <675000 675000 850000>, + <675000 675000 850000>; + opp-microvolt-L0 = <725000 725000 850000>, + <725000 725000 850000>; + opp-microvolt-L1 = <712500 712500 850000>, + <712500 712500 850000>; + opp-microvolt-L2 = <712500 712500 850000>, + <712500 712500 850000>; + opp-microvolt-L3 = <700000 700000 850000>, + <700000 700000 850000>; + opp-microvolt-L4 = <687500 687500 850000>, + <687500 687500 850000>; + }; + opp-b-700000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = /bits/ 64 <700000000>; + opp-microvolt = <737500 737500 850000>, + <737500 737500 850000>; + opp-microvolt-L1 = <725000 725000 850000>, + <725000 725000 850000>; + opp-microvolt-L2 = <712500 712500 850000>, + <712500 712500 850000>; + opp-microvolt-L3 = <700000 700000 850000>, + <700000 700000 850000>; + opp-microvolt-L4 = <700000 700000 850000>, + <700000 700000 850000>; + opp-microvolt-L5 = <687500 687500 850000>, + <687500 687500 850000>; + opp-microvolt-L6 = <687500 687500 850000>, + <687500 687500 850000>; + opp-microvolt-L7 = <675000 675000 850000>, + <675000 675000 850000>; + opp-microvolt-L8 = <675000 675000 850000>, + <675000 675000 850000>; + }; + opp-b-800000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <787500 787500 850000>, + <787500 787500 850000>; + opp-microvolt-L1 = <775000 775000 850000>, + <775000 775000 850000>; + opp-microvolt-L2 = <762500 762500 850000>, + <762500 762500 850000>; + opp-microvolt-L3 = <750000 750000 850000>, + <750000 750000 850000>; + opp-microvolt-L4 = <750000 750000 850000>, + <750000 750000 850000>; + opp-microvolt-L5 = <737500 737500 850000>, + <737500 737500 850000>; + opp-microvolt-L6 = <725000 725000 850000>, + <725000 725000 850000>; + opp-microvolt-L7 = <712500 712500 850000>, + <712500 712500 850000>; + opp-microvolt-L8 = <700000 700000 850000>, + <700000 700000 850000>; + }; + opp-950000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = /bits/ 64 <950000000>; + opp-microvolt = <850000 850000 850000>, + <850000 850000 850000>; + opp-microvolt-L2 = <850000 850000 850000>, + <850000 850000 850000>; + opp-microvolt-L3 = <837500 837500 850000>, + <837500 837500 850000>; + opp-microvolt-L4 = <825000 825000 850000>, + <825000 825000 850000>; + opp-microvolt-L5 = <812500 812500 850000>, + <812500 812500 850000>; + opp-microvolt-L6 = <800000 800000 850000>, + <800000 800000 850000>; + opp-microvolt-L7 = <787500 787500 850000>, + <787500 787500 850000>; + opp-microvolt-L8 = <775000 775000 850000>, + <775000 775000 850000>; + }; + /* RK3588J/M npu OPPs */ opp-j-m-300000000 { opp-supported-hw = <0x06 0xffff>; @@ -6675,6 +7480,10 @@ gpu_leakage: gpu-leakage@1b { reg = <0x1b 0x1>; }; + customer_demand: customer-demand@22 { + reg = <0x22 0x1>; + bits = <4 4>; + }; npu_leakage: npu-leakage@28 { reg = <0x28 0x1>; }; diff --git a/drivers/cpufreq/rockchip-cpufreq.c b/drivers/cpufreq/rockchip-cpufreq.c index d28c338fec39..9e7566ea5b35 100644 --- a/drivers/cpufreq/rockchip-cpufreq.c +++ b/drivers/cpufreq/rockchip-cpufreq.c @@ -240,6 +240,15 @@ static int rk3588_get_soc_info(struct device *dev, struct device_node *np, else if (value == 0xa) *bin = 2; } + if (of_property_match_string(np, "nvmem-cell-names", "customer_demand") >= 0) { + ret = rockchip_nvmem_cell_read_u8(np, "customer_demand", &value); + if (ret) { + dev_err(dev, "Failed to get customer_demand\n"); + return ret; + } + if (value == 0x3) + *bin = 4; + } if (*bin < 0) *bin = 0; dev_info(dev, "bin=%d\n", *bin); diff --git a/drivers/firmware/rockchip_sip.c b/drivers/firmware/rockchip_sip.c index b426ec3d4977..8a2e82c73fde 100644 --- a/drivers/firmware/rockchip_sip.c +++ b/drivers/firmware/rockchip_sip.c @@ -371,6 +371,15 @@ struct arm_smccc_res sip_smc_gpio_config(u32 sub_func_id, u32 arg1, u32 arg2, } EXPORT_SYMBOL_GPL(sip_smc_gpio_config); +int sip_smc_cpu_pm_config(u32 func, u32 id, u32 cfg) +{ + struct arm_smccc_res res; + + res = __invoke_sip_fn_smc(SIP_CPU_PM_CFG, func, id, cfg); + return res.a0; +} +EXPORT_SYMBOL_GPL(sip_smc_cpu_pm_config); + /************************** fiq debugger **************************************/ /* * AArch32 is not allowed to call SMC64(ATF framework does not support), so we diff --git a/drivers/gpu/arm/bifrost/platform/rk/mali_kbase_config_rk.c b/drivers/gpu/arm/bifrost/platform/rk/mali_kbase_config_rk.c index d20de78ce478..baec96532353 100755 --- a/drivers/gpu/arm/bifrost/platform/rk/mali_kbase_config_rk.c +++ b/drivers/gpu/arm/bifrost/platform/rk/mali_kbase_config_rk.c @@ -553,6 +553,15 @@ static int rk3588_gpu_get_soc_info(struct device *dev, struct device_node *np, else if (value == 0xa) *bin = 2; } + if (of_property_match_string(np, "nvmem-cell-names", "customer_demand") >= 0) { + ret = rockchip_nvmem_cell_read_u8(np, "customer_demand", &value); + if (ret) { + dev_err(dev, "Failed to get customer_demand\n"); + return ret; + } + if (value == 0x3) + *bin = 4; + } if (*bin < 0) *bin = 0; dev_info(dev, "bin=%d\n", *bin); diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c index fc7fc9c77af1..2da90d89cf3c 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -2466,8 +2466,8 @@ dw_hdmi_rockchip_select_output(struct drm_connector_state *conn_state, *enc_out_encoding = V4L2_YCBCR_ENC_BT2020; yuv422_out = true; /* bt709 hdr output */ - } else if ((hdmi->colorimetry <= DRM_MODE_COLORIMETRY_BT2020_CYCC) && - (hdmi->colorimetry >= DRM_MODE_COLORIMETRY_BT2020_YCC) && + } else if (((hdmi->colorimetry <= DRM_MODE_COLORIMETRY_BT2020_CYCC) || + (hdmi->colorimetry >= DRM_MODE_COLORIMETRY_BT2020_YCC)) && (conn_state->connector->hdr_sink_metadata.hdmi_type1.eotf & BIT(*eotf) && *eotf > HDMI_EOTF_TRADITIONAL_GAMMA_SDR)) { *enc_out_encoding = V4L2_YCBCR_ENC_709; diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c index 3b7540034c89..f81c53bbfe50 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c @@ -1858,7 +1858,6 @@ static DEVICE_ATTR(error_event, 0444, rockchip_drm_error_event_show, NULL); static void rockchip_drm_error_event_init(struct drm_device *drm_dev) { struct rockchip_drm_private *priv = drm_dev->dev_private; - struct sched_param sched_param = { .sched_priority = MAX_RT_PRIO - 1 }; int ret; ret = device_create_file(drm_dev->dev, &dev_attr_error_event); @@ -1875,7 +1874,7 @@ static void rockchip_drm_error_event_init(struct drm_device *drm_dev) priv->error_event.thread = NULL; drm_err(drm_dev, "failed to run display error_event thread\n"); } else { - sched_setscheduler(priv->error_event.thread, SCHED_FIFO, &sched_param); + sched_set_fifo_low(priv->error_event.thread); drm_info(drm_dev, "run display error_event monitor\n"); } } diff --git a/drivers/media/platform/rockchip/cif/capture.c b/drivers/media/platform/rockchip/cif/capture.c index 875ba821f007..991913018228 100644 --- a/drivers/media/platform/rockchip/cif/capture.c +++ b/drivers/media/platform/rockchip/cif/capture.c @@ -12925,6 +12925,8 @@ static void rkcif_toisp_check_stop_status(struct sditf_priv *priv, u64 cur_time = 0; int on = 0; unsigned long flags; + struct v4l2_subdev *sd = NULL; + struct rkisp_vicap_sof sof = {0}; for (i = 0; i < TOISP_CH_MAX; i++) { if (priv->cif_dev->chip_id < CHIP_RK3576_CIF) @@ -13052,6 +13054,16 @@ static void rkcif_toisp_check_stop_status(struct sditf_priv *priv, stream = &priv->cif_dev->stream[src_id % 4]; if (priv->cif_dev->chip_id < CHIP_RK3576_CIF) { if (stream->id == 0) { + spin_lock_irqsave(&stream->fps_lock, flags); + stream->readout.fs_timestamp = rkcif_time_get_ns(priv->cif_dev); + spin_unlock_irqrestore(&stream->fps_lock, flags); + rkcif_add_sensor_exp_to_kfifo(&priv->cif_dev->stream[0]); + sd = get_rkisp_sd(priv->cif_dev->sditf[0]); + if (sd) { + rkcif_get_sof_and_exp_info(priv->cif_dev, &sof); + v4l2_subdev_call(sd, core, ioctl, + RKISP_VICAP_CMD_SOF, &sof); + } spin_lock_irqsave(&stream->vbq_lock, flags); if ((!stream->thunderboot_skip_interval || (stream->thunderboot_skip_interval && @@ -13220,14 +13232,12 @@ static void rkcif_deal_sof(struct rkcif_device *cif_dev) detect_stream->readout.fs_timestamp = rkcif_time_get_ns(cif_dev); spin_unlock_irqrestore(&detect_stream->fps_lock, flags); - if (cif_dev->chip_id >= CHIP_RK3576_CIF) { - rkcif_add_sensor_exp_to_kfifo(&cif_dev->stream[0]); - sd = get_rkisp_sd(cif_dev->sditf[0]); - if (sd) { - rkcif_get_sof_and_exp_info(cif_dev, &sof); - v4l2_subdev_call(sd, core, ioctl, - RKISP_VICAP_CMD_SOF, &sof); - } + rkcif_add_sensor_exp_to_kfifo(&cif_dev->stream[0]); + sd = get_rkisp_sd(cif_dev->sditf[0]); + if (sd) { + rkcif_get_sof_and_exp_info(cif_dev, &sof); + v4l2_subdev_call(sd, core, ioctl, + RKISP_VICAP_CMD_SOF, &sof); } if (cif_dev->chip_id < CHIP_RK3588_CIF) @@ -13952,22 +13962,22 @@ void rkcif_err_print_work(struct work_struct *work) if (err_state & RKCIF_ERR_SIZE) { if (dev->chip_id >= CHIP_RK3588_CIF) v4l2_err(&dev->v4l2_dev, - "ERROR: csi size err, intstat:0x%x, size:0x%x,0x%x,0x%x,0x%x, cnt %llu\n", + "ERROR: size err, intstat:0x%x, size:0x%x,0x%x,0x%x,0x%x, cnt %llu\n", intstat, err_state_work->size_id0, err_state_work->size_id1, err_state_work->size_id2, err_state_work->size_id3, dev->irq_stats.csi_size_err_cnt); else v4l2_err(&dev->v4l2_dev, - "ERROR: csi size err, intstat:0x%x, lastline:0x%x, cnt %llu\n", + "ERROR: size err, intstat:0x%x, lastline:0x%x, cnt %llu\n", intstat, lastline, dev->irq_stats.csi_size_err_cnt); } if (err_state & RKCIF_ERR_OVERFLOW) v4l2_err(&dev->v4l2_dev, - "ERROR: csi fifo overflow, intstat:0x%x, lastline:0x%x, cnt %llu\n", + "ERROR: fifo overflow, intstat:0x%x, lastline:0x%x, cnt %llu\n", intstat, lastline, dev->irq_stats.csi_overflow_cnt); if (err_state & RKCIF_ERR_BANDWIDTH_LACK) v4l2_err(&dev->v4l2_dev, - "ERROR: csi bandwidth lack, intstat:0x%x, lastline:0x%x, cnt %llu\n", + "ERROR: bandwidth lack, intstat:0x%x, lastline:0x%x, cnt %llu\n", intstat, lastline, dev->irq_stats.csi_bwidth_lack_cnt); if (err_state & RKCIF_ERR_ID0_MULTI_FS) v4l2_err(&dev->v4l2_dev, diff --git a/drivers/media/platform/rockchip/cif/hw.c b/drivers/media/platform/rockchip/cif/hw.c index b35dff32fe97..6b79064147a4 100644 --- a/drivers/media/platform/rockchip/cif/hw.c +++ b/drivers/media/platform/rockchip/cif/hw.c @@ -1062,6 +1062,10 @@ static const struct cif_reg rk3576_cif_regs[] = { [CIF_REG_MIPI_SET_SIZE_ID1] = CIF_REG(CSI_MIPI0_SET_FRAME_SIZE_ID1_RK3576), [CIF_REG_MIPI_SET_SIZE_ID2] = CIF_REG(CSI_MIPI0_SET_FRAME_SIZE_ID2_RK3576), [CIF_REG_MIPI_SET_SIZE_ID3] = CIF_REG(CSI_MIPI0_SET_FRAME_SIZE_ID3_RK3576), + [CIF_REG_MIPI_FRAME_SIZE_ID0] = CIF_REG(CSI_MIPI0_FRAME_SIZE_ID0), + [CIF_REG_MIPI_FRAME_SIZE_ID1] = CIF_REG(CSI_MIPI0_FRAME_SIZE_ID1), + [CIF_REG_MIPI_FRAME_SIZE_ID2] = CIF_REG(CSI_MIPI0_FRAME_SIZE_ID2), + [CIF_REG_MIPI_FRAME_SIZE_ID3] = CIF_REG(CSI_MIPI0_FRAME_SIZE_ID3), [CIF_REG_GLB_CTRL] = CIF_REG(GLB_CTRL), [CIF_REG_GLB_INTEN] = CIF_REG(GLB_INTEN), @@ -1147,6 +1151,10 @@ static const struct cif_reg rv1103b_cif_regs[] = { [CIF_REG_MIPI_SET_SIZE_ID1] = CIF_REG(CSI_MIPI0_SET_FRAME_SIZE_ID1_RK3576), [CIF_REG_MIPI_SET_SIZE_ID2] = CIF_REG(CSI_MIPI0_SET_FRAME_SIZE_ID2_RK3576), [CIF_REG_MIPI_SET_SIZE_ID3] = CIF_REG(CSI_MIPI0_SET_FRAME_SIZE_ID3_RK3576), + [CIF_REG_MIPI_FRAME_SIZE_ID0] = CIF_REG(CSI_MIPI0_FRAME_SIZE_ID0), + [CIF_REG_MIPI_FRAME_SIZE_ID1] = CIF_REG(CSI_MIPI0_FRAME_SIZE_ID1), + [CIF_REG_MIPI_FRAME_SIZE_ID2] = CIF_REG(CSI_MIPI0_FRAME_SIZE_ID2), + [CIF_REG_MIPI_FRAME_SIZE_ID3] = CIF_REG(CSI_MIPI0_FRAME_SIZE_ID3), [CIF_REG_GLB_CTRL] = CIF_REG(GLB_CTRL), [CIF_REG_GLB_INTEN] = CIF_REG(GLB_INTEN), diff --git a/drivers/media/platform/rockchip/cif/procfs.c b/drivers/media/platform/rockchip/cif/procfs.c index e6acb53607e4..83fbb65c9de3 100644 --- a/drivers/media/platform/rockchip/cif/procfs.c +++ b/drivers/media/platform/rockchip/cif/procfs.c @@ -390,14 +390,14 @@ static void rkcif_show_reg_csi2(struct rkcif_device *dev, struct seq_file *f) struct csi2_hw *csi2_hw = NULL; int i, j; int csi_idx = 0; - u32 buf[20]; + u32 buf[24]; for (j = 0; j < csi2->csi_info.csi_num; j++) { csi_idx = csi2->csi_info.csi_idx[j]; csi2_hw = csi2->csi2_hw[csi_idx]; seq_printf(f, "\nmipi%d csi2 reg:\n", csi_idx); - memcpy_fromio(buf, csi2_hw->base, 0x50); - for (i = 0; i < 0x50 / 16; i++) + memcpy_fromio(buf, csi2_hw->base, 0x60); + for (i = 0; i < 0x60 / 16; i++) seq_printf(f, "0x%x: 0x%08x 0x%08x 0x%08x 0x%08x\n", (u32)(csi2_hw->res->start + i * 16), *(buf + i * 4), *(buf + i * 4 + 1), @@ -491,6 +491,16 @@ static void rkcif_show_reg_dphys(struct rkcif_device *dev, struct seq_file *f) if (dphy_hw) rkcif_show_reg_dphy(dphy_hw, (csi_idx - 2) / 2, f); } + } else if (dphy->drv_data->chip_id == CHIP_ID_RK3576) { + if (csi_idx < 1) { + dcphy_hw = dphy->samsung_phy_group[csi_idx]; + if (dcphy_hw) + rkcif_show_reg_dcphy(dcphy_hw, csi_idx, f); + } else { + dphy_hw = dphy->dphy_hw_group[(csi_idx - 1) / 2]; + if (dphy_hw) + rkcif_show_reg_dphy(dphy_hw, (csi_idx - 1) / 2, f); + } } else { dphy_hw = dphy->dphy_hw_group[csi_idx / 2]; if (dphy_hw) @@ -507,7 +517,7 @@ static void rkcif_show_reg_dbg(struct rkcif_device *dev, struct seq_file *f) if (dev->inf_id == RKCIF_MIPI_LVDS) { if (dev->active_sensor->mbus.type == V4L2_MBUS_CSI2_DPHY || dev->active_sensor->mbus.type == V4L2_MBUS_CSI2_CPHY) { - for (i = 0; i < 5; i++) { + for (i = 0; i < 10; i++) { rkcif_show_reg_csi2(dev, f); usleep_range(2000, 4000); } diff --git a/drivers/rknpu/rknpu_devfreq.c b/drivers/rknpu/rknpu_devfreq.c index 5d87fa40e79f..e7756f4e4e90 100644 --- a/drivers/rknpu/rknpu_devfreq.c +++ b/drivers/rknpu/rknpu_devfreq.c @@ -120,6 +120,15 @@ static int rk3588_npu_get_soc_info(struct device *dev, struct device_node *np, else if (value == 0xa) *bin = 2; } + if (of_property_match_string(np, "nvmem-cell-names", "customer_demand") >= 0) { + ret = rockchip_nvmem_cell_read_u8(np, "customer_demand", &value); + if (ret) { + dev_err(dev, "Failed to get customer_demand\n"); + return ret; + } + if (value == 0x3) + *bin = 4; + } if (*bin < 0) *bin = 0; LOG_DEV_INFO(dev, "bin=%d\n", *bin); diff --git a/drivers/soc/rockchip/rockchip_opp_select.c b/drivers/soc/rockchip/rockchip_opp_select.c index e7f0644600b4..1e3428854568 100644 --- a/drivers/soc/rockchip/rockchip_opp_select.c +++ b/drivers/soc/rockchip/rockchip_opp_select.c @@ -1353,6 +1353,16 @@ static int rockchip_get_soc_info(struct device *dev, struct device_node *np, else if (value == 0x13) *bin = 3; + if (of_property_match_string(np, "nvmem-cell-names", "customer_demand") >= 0) { + ret = rockchip_nvmem_cell_read_u8(np, "customer_demand", &value); + if (ret) { + dev_err(dev, "Failed to get customer_demand\n"); + return ret; + } + if (value == 0x3) + *bin = 4; + } + if (*bin < 0) *bin = 0; dev_info(dev, "bin=%d\n", *bin); diff --git a/include/linux/rockchip/rockchip_sip.h b/include/linux/rockchip/rockchip_sip.h index b6196c138698..0ebcb2fae62d 100644 --- a/include/linux/rockchip/rockchip_sip.h +++ b/include/linux/rockchip/rockchip_sip.h @@ -60,6 +60,7 @@ #define SIP_MCU_CFG 0x82000028 #define SIP_PVTPLL_CFG 0x82000029 #define SIP_GPIO_CFG 0x8200002c +#define SIP_CPU_PM_CFG 0x8200002d #define TRUSTED_OS_HDCPKEY_INIT 0xB7000003 @@ -257,6 +258,11 @@ enum { GPIO_GET_VIRT_EN = 2, }; +/* SIP_CPU_PM_CFG child configs */ +enum { + CPU_PM_CLUST_AUTO_PD_EN = 0, +}; + struct pt_regs; typedef void (*sip_fiq_debugger_uart_irq_tf_cb_t)(struct pt_regs *_pt_regs, unsigned long cpu); @@ -296,6 +302,7 @@ void __iomem *sip_hdcp_request_share_memory(int id); struct arm_smccc_res sip_hdcp_config(u32 arg0, u32 arg1, u32 arg2); struct arm_smccc_res sip_smc_gpio_config(u32 sub_func_id, u32 arg1, u32 arg2, u32 arg3); +int sip_smc_cpu_pm_config(u32 func, u32 id, u32 cfg); ulong sip_cpu_logical_map_mpidr(u32 cpu); /***************************fiq debugger **************************************/ void sip_fiq_debugger_enable_fiq(bool enable, uint32_t tgt_cpu); @@ -447,6 +454,11 @@ static inline struct arm_smccc_res sip_smc_gpio_config(u32 sub_func_id, u32 arg1 return tmp; } +static inline int sip_smc_cpu_pm_config(u32 func, u32 id, u32 cfg) +{ + return SIP_RET_NOT_SUPPORTED; +} + static inline ulong sip_cpu_logical_map_mpidr(u32 cpu) { return 0; } /***************************fiq debugger **************************************/