diff --git a/drivers/pci/controller/dwc/pcie-dw-ep-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-ep-rockchip.c
index 6949ef902bff..2b19e0eed47f 100644
--- a/drivers/pci/controller/dwc/pcie-dw-ep-rockchip.c
+++ b/drivers/pci/controller/dwc/pcie-dw-ep-rockchip.c
@@ -423,6 +423,11 @@ static void rockchip_pcie_resize_bar_nsticky(struct rockchip_pcie *rockchip)
 	dw_pcie_writel_dbi(pci, resbar_base + 0x8 + bar * 0x8, 0x2c0);
 	rockchip_pcie_ep_set_bar_flag(rockchip, bar, PCI_BASE_ADDRESS_MEM_TYPE_32);
 
+	bar = BAR_1;
+	dw_pcie_writel_dbi(pci, resbar_base + 0x4 + bar * 0x8, 0x10);
+	dw_pcie_writel_dbi(pci, resbar_base + 0x8 + bar * 0x8, 0xc0);
+	rockchip_pcie_ep_set_bar_flag(rockchip, bar, PCI_BASE_ADDRESS_MEM_TYPE_32);
+
 	bar = BAR_2;
 	dw_pcie_writel_dbi(pci, resbar_base + 0x4 + bar * 0x8, 0x400);
 	dw_pcie_writel_dbi(pci, resbar_base + 0x8 + bar * 0x8, 0x6c0);
@@ -434,11 +439,18 @@ static void rockchip_pcie_resize_bar_nsticky(struct rockchip_pcie *rockchip)
 	dw_pcie_writel_dbi(pci, resbar_base + 0x8 + bar * 0x8, 0xc0);
 	rockchip_pcie_ep_set_bar_flag(rockchip, bar, PCI_BASE_ADDRESS_MEM_TYPE_32);
 
+	bar = BAR_5;
+	dw_pcie_writel_dbi(pci, resbar_base + 0x4 + bar * 0x8, 0x10);
+	dw_pcie_writel_dbi(pci, resbar_base + 0x8 + bar * 0x8, 0xc0);
+	rockchip_pcie_ep_set_bar_flag(rockchip, bar, PCI_BASE_ADDRESS_MEM_TYPE_32);
+
 	/* Disable BAR1 BAR5*/
 	bar = BAR_1;
-	dw_pcie_writel_dbi(pci, PCIE_TYPE0_HDR_DBI2_OFFSET + 0x10 + bar * 4, 0);
+	if (!rockchip->ib_target_size[bar])
+		dw_pcie_writel_dbi(pci, PCIE_TYPE0_HDR_DBI2_OFFSET + 0x10 + bar * 4, 0);
 	bar = BAR_5;
-	dw_pcie_writel_dbi(pci, PCIE_TYPE0_HDR_DBI2_OFFSET + 0x10 + bar * 4, 0);
+	if (!rockchip->ib_target_size[bar])
+		dw_pcie_writel_dbi(pci, PCIE_TYPE0_HDR_DBI2_OFFSET + 0x10 + bar * 4, 0);
 	dw_pcie_dbi_ro_wr_dis(&rockchip->pci);
 }
 
@@ -1157,6 +1169,13 @@ static int pcie_ep_mmap(struct file *file, struct vm_area_struct *vma)
 		}
 		addr = rockchip->ib_target_address[0];
 		break;
+	case PCIE_EP_MMAP_RESOURCE_BAR1:
+		if (size > rockchip->ib_target_size[1]) {
+			dev_warn(rockchip->pci.dev, "bar1 mmap size is out of limitation\n");
+			return -EINVAL;
+		}
+		addr = rockchip->ib_target_address[1];
+		break;
 	case PCIE_EP_MMAP_RESOURCE_BAR2:
 		if (size > rockchip->ib_target_size[2]) {
 			dev_warn(rockchip->pci.dev, "bar2 mmap size is out of limitation\n");
@@ -1164,6 +1183,13 @@ static int pcie_ep_mmap(struct file *file, struct vm_area_struct *vma)
 		}
 		addr = rockchip->ib_target_address[2];
 		break;
+	case PCIE_EP_MMAP_RESOURCE_BAR5:
+		if (size > rockchip->ib_target_size[5]) {
+			dev_warn(rockchip->pci.dev, "bar5 mmap size is out of limitation\n");
+			return -EINVAL;
+		}
+		addr = rockchip->ib_target_address[5];
+		break;
 	default:
 		dev_err(rockchip->pci.dev, "cur mmap_res %d is unsurreport\n", rockchip->cur_mmap_res);
 		return -EINVAL;