From e35fd036b3041ba2982cd04aaa51814f7f7ac553 Mon Sep 17 00:00:00 2001 From: Randy Li Date: Fri, 20 Oct 2017 14:38:09 +0800 Subject: [PATCH] clk: rockchip: rk3036: export the hevc core clock The clock hevc core will be used to drive the hevc decoder. Change-Id: Ic1298ce1edd07f86e5c243e3a2c9876481f4cba9 Signed-off-by: Randy Li Signed-off-by: Elaine Zhang --- drivers/clk/rockchip/clk-rk3036.c | 5 ++++- include/dt-bindings/clock/rk3036-cru.h | 1 + 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/clk/rockchip/clk-rk3036.c b/drivers/clk/rockchip/clk-rk3036.c index b453a69a7e75..5d0813df2f76 100644 --- a/drivers/clk/rockchip/clk-rk3036.c +++ b/drivers/clk/rockchip/clk-rk3036.c @@ -101,8 +101,11 @@ static struct rockchip_pll_rate_table rk3036_pll_rates[] = { } static struct rockchip_cpuclk_rate_table rk3036_cpuclk_rates[] __initdata = { + RK3036_CPUCLK_RATE(1200000000, 4), + RK3036_CPUCLK_RATE(1008000000, 4), RK3036_CPUCLK_RATE(816000000, 4), RK3036_CPUCLK_RATE(600000000, 4), + RK3036_CPUCLK_RATE(408000000, 4), RK3036_CPUCLK_RATE(312000000, 4), }; @@ -270,7 +273,7 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = { FACTOR_GATE(HCLK_VCODEC, "hclk_vcodec", "aclk_vcodec", 0, 1, 4, RK2928_CLKGATE_CON(3), 12, GFLAGS), - COMPOSITE(0, "aclk_hvec", mux_pll_src_3plls_p, 0, + COMPOSITE(ACLK_HEVC, "aclk_hevc", mux_pll_src_3plls_p, 0, RK2928_CLKSEL_CON(20), 0, 2, MFLAGS, 2, 5, DFLAGS, RK2928_CLKGATE_CON(10), 6, GFLAGS), diff --git a/include/dt-bindings/clock/rk3036-cru.h b/include/dt-bindings/clock/rk3036-cru.h index 35a5a01f9697..cd231f57278d 100644 --- a/include/dt-bindings/clock/rk3036-cru.h +++ b/include/dt-bindings/clock/rk3036-cru.h @@ -55,6 +55,7 @@ #define ACLK_VCODEC 208 #define ACLK_CPU 209 #define ACLK_PERI 210 +#define ACLK_HEVC 211 /* pclk gates */ #define PCLK_GPIO0 320