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rk3288: clk: isp: set isp aclk and hclk from same source.

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Because isp aclk and hclk from same source,
	So vio aclk and hclk from same source.

Signed-off-by: zhangqing <zhangqing@rock-chips.com>
This commit is contained in:
zhangqing
2015-05-04 10:10:31 +08:00
parent f3a6eaaee4
commit e3eff0c124
2 changed files with 17 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
arch/arm/boot/dts/rk3288.dtsi
View File

@@ -493,8 +493,8 @@
<&hclk_bus 150000000>, <&pclk_bus 75000000>,
<&clk_crypto 150000000>, <&aclk_peri 300000000>,
<&hclk_peri 150000000>, <&pclk_peri 75000000>,
<&clk_gpu 200000000>, <&aclk_vio0 300000000>,
<&aclk_vio1 300000000>, <&hclk_vio 75000000>,
<&clk_gpu 200000000>, /*<&aclk_vio0 300000000>,
<&aclk_vio1 300000000>, <&hclk_vio 75000000>,*/
<&pclk_pd_alive 100000000>, <&pclk_pd_pmu 100000000>,
<&aclk_hevc 400000000>, <&hclk_hevc 200000000>,
<&clk_hevc_cabac 300000000>, <&clk_hevc_core 300000000>,
@@ -503,8 +503,8 @@
<&clk_edp 200000000>, <&clk_isp 200000000>,
<&clk_isp_jpe 400000000>, <&clk_tsp 80000000>,
<&clk_tspout 80000000>, <&clk_mac 125000000>;
rockchip,clocks-uboot-has-init =
<&aclk_vio0>;
/* rockchip,clocks-uboot-has-init =
<&aclk_vio0>; */
};
clocks-enable {

15
drivers/clk/rockchip/clk-ops.c
View File

@@ -7,6 +7,7 @@
#include <linux/clk-private.h>
#include <linux/delay.h>
#include <linux/rockchip/common.h>
#include <linux/rockchip/cpu.h>
#include "clk-ops.h"
@@ -613,6 +614,7 @@ static int clk_3288_dclk_lcdc0_set_rate(struct clk_hw *hw, unsigned long rate,
{
struct clk* aclk_vio0 = clk_get(NULL, "aclk_vio0");
struct clk* hclk_vio = clk_get(NULL, "hclk_vio");
struct clk *aclk_vio1;
struct clk* parent;
clk_divider_ops.set_rate(hw, rate, parent_rate);
@@ -627,6 +629,13 @@ static int clk_3288_dclk_lcdc0_set_rate(struct clk_hw *hw, unsigned long rate,
clk_set_rate(aclk_vio0, __clk_get_rate(parent));
clk_set_rate(hclk_vio, 100*MHZ);
/* make aclk_isp and hclk_isp share a same pll in rk3288_eco */
if (rockchip_get_cpu_version() > 0) {
aclk_vio1 = clk_get(NULL, "aclk_vio1");
clk_set_parent(aclk_vio1, parent);
clk_set_rate(aclk_vio1, __clk_get_rate(parent));
}
return 0;
}
@@ -683,8 +692,10 @@ static int clk_3288_dclk_lcdc1_set_rate(struct clk_hw *hw, unsigned long rate,
else
parent = clk_get(NULL, "clk_cpll");
clk_set_parent(aclk_vio1, parent);
clk_set_rate(aclk_vio1, __clk_get_rate(parent));
if (rockchip_get_cpu_version() == 0) {
clk_set_parent(aclk_vio1, parent);
clk_set_rate(aclk_vio1, __clk_get_rate(parent));
}
return 0;
}