From e42f67144763bbbd99e1a56f29d5ce6b167624c6 Mon Sep 17 00:00:00 2001 From: Zefa Chen Date: Tue, 21 Feb 2023 15:26:53 +0800 Subject: [PATCH] arm64: dts: rockchip: rk3562: vicap add csirx data clk control Signed-off-by: Zefa Chen Change-Id: I15baadf44db6c1325812b925e7ac84c636f6303c --- arch/arm64/boot/dts/rockchip/rk3562.dtsi | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3562.dtsi b/arch/arm64/boot/dts/rockchip/rk3562.dtsi index f22152bd47af..339567802cb4 100644 --- a/arch/arm64/boot/dts/rockchip/rk3562.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3562.dtsi @@ -1422,8 +1422,12 @@ reg-names = "cif_regs"; interrupts = ; interrupt-names = "cif-intr"; - clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>, <&cru DCLK_VICAP>; - clock-names = "aclk_cif", "hclk_cif", "dclk_cif"; + clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>, <&cru DCLK_VICAP>, + <&cru CSIRX0_CLK_DATA>, <&cru CSIRX1_CLK_DATA>, + <&cru CSIRX2_CLK_DATA>, <&cru CSIRX3_CLK_DATA>; + clock-names = "aclk_cif", "hclk_cif", "dclk_cif", + "csirx0_data", "csirx1_data", "csirx2_data", + "csirx3_data"; resets = <&cru SRST_A_VICAP>, <&cru SRST_H_VICAP>, <&cru SRST_D_VICAP>, <&cru SRST_I0_VICAP>, <&cru SRST_I1_VICAP>, <&cru SRST_I2_VICAP>, <&cru SRST_I3_VICAP>;