From e4899cdc78ff52667659f7b773b0070367948c0a Mon Sep 17 00:00:00 2001
From: Finley Xiao <finley.xiao@rock-chips.com>
Date: Thu, 11 Nov 2021 23:31:08 +0800
Subject: [PATCH] Revert "arm64: dts: rockchip: rk3588: Add pd vdpu before pd
 rkvdec"

This reverts commit 24627eab36579c0976341d24a01c5aad097ad735.

Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: I8308cffccadcb7f585ee19b39f2575477ae0d62b
---
 arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 66 +++++++++++++----------
 1 file changed, 38 insertions(+), 28 deletions(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
index a104ddd717ca..d2a58d40fbf8 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -726,34 +726,6 @@
 					 <&qos_gpu_m2>,
 					 <&qos_gpu_m3>;
 			};
-
-			/* These power domains are grouped by VD_LOGIC */
-			power-domain@RK3588_PD_VDPU {
-				reg = <RK3588_PD_VDPU>;
-				#address-cells = <1>;
-				#size-cells = <0>;
-				clocks = <&cru HCLK_VDPU_ROOT>;
-				pm_qos = <&qos_iep>,
-					 <&qos_jpeg_dec>,
-					 <&qos_jpeg_enc0>,
-					 <&qos_jpeg_enc1>,
-					 <&qos_jpeg_enc2>,
-					 <&qos_jpeg_enc3>,
-					 <&qos_rga2_mro>,
-					 <&qos_rga2_mwo>;
-
-				power-domain@RK3588_PD_AV1 {
-					reg = <RK3588_PD_AV1>;
-					clocks = <&cru PCLK_AV1_ROOT>,
-						 <&cru HCLK_VDPU_ROOT>;
-					pm_qos = <&qos_av1>;
-				};
-				power-domain@RK3588_PD_RGA30 {
-					reg = <RK3588_PD_RGA30>;
-					clocks = <&cru HCLK_VDPU_ROOT>;
-					pm_qos = <&qos_rga3_0>;
-				};
-			};
 			/* These power domains are grouped by VD_VCODEC */
 			power-domain@RK3588_PD_VCODEC {
 				reg = <RK3588_PD_VCODEC>;
@@ -791,7 +763,45 @@
 					};
 				};
 			};
+			/* These power domains are grouped by VD_LOGIC */
+			power-domain@RK3588_PD_VDPU {
+				reg = <RK3588_PD_VDPU>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks = <&cru HCLK_VDPU_ROOT>;
+				pm_qos = <&qos_iep>,
+					 <&qos_jpeg_dec>,
+					 <&qos_jpeg_enc0>,
+					 <&qos_jpeg_enc1>,
+					 <&qos_jpeg_enc2>,
+					 <&qos_jpeg_enc3>,
+					 <&qos_rga2_mro>,
+					 <&qos_rga2_mwo>;
 
+				power-domain@RK3588_PD_AV1 {
+					reg = <RK3588_PD_AV1>;
+					clocks = <&cru PCLK_AV1_ROOT>,
+						 <&cru HCLK_VDPU_ROOT>;
+					pm_qos = <&qos_av1>;
+				};
+				power-domain@RK3588_PD_RKVDEC0 {
+					reg = <RK3588_PD_RKVDEC0>;
+					clocks = <&cru HCLK_RKVDEC0>,
+						 <&cru HCLK_VDPU_ROOT>;
+					pm_qos = <&qos_rkvdec0>;
+				};
+				power-domain@RK3588_PD_RKVDEC1 {
+					reg = <RK3588_PD_RKVDEC1>;
+					clocks = <&cru HCLK_RKVDEC1>,
+						 <&cru HCLK_VDPU_ROOT>;
+					pm_qos = <&qos_rkvdec1>;
+				};
+				power-domain@RK3588_PD_RGA30 {
+					reg = <RK3588_PD_RGA30>;
+					clocks = <&cru HCLK_VDPU_ROOT>;
+					pm_qos = <&qos_rga3_0>;
+				};
+			};
 			power-domain@RK3588_PD_VOP {
 				reg = <RK3588_PD_VOP>;
 				#address-cells = <1>;