From e5277633c625446046d437f9d580a7364355c28c Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Fri, 12 Nov 2021 09:27:57 +0800 Subject: [PATCH] clk: rockchip: rk3588: add 786M for AUPLL init Signed-off-by: Elaine Zhang Change-Id: Ic9b76bc29cf07593a94deaeeaaecd81d5bdbd649 --- drivers/clk/rockchip/clk-rk3588.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/rockchip/clk-rk3588.c b/drivers/clk/rockchip/clk-rk3588.c index 6768196e78c1..df851a55a21b 100644 --- a/drivers/clk/rockchip/clk-rk3588.c +++ b/drivers/clk/rockchip/clk-rk3588.c @@ -78,6 +78,7 @@ static struct rockchip_pll_rate_table rk3588_pll_rates[] = { RK3588_PLL_RATE(1000000000, 3, 500, 2, 0), RK3588_PLL_RATE(900000000, 2, 300, 2, 0), RK3588_PLL_RATE(816000000, 2, 272, 2, 0), + RK3588_PLL_RATE(786000000, 1, 131, 2, 0), RK3588_PLL_RATE(600000000, 2, 200, 2, 0), RK3588_PLL_RATE(594000000, 2, 198, 2, 0), RK3588_PLL_RATE(408000000, 2, 272, 3, 0),