From e56c051873fa5aee1af101f171975dd33aa0406c Mon Sep 17 00:00:00 2001 From: Shunzhou Jiang Date: Tue, 14 May 2019 09:47:43 +0800 Subject: [PATCH] clk: sm1: add sm1 dsu clk notify for change dsu freq [1/1] PD#SWPL-8145 Problem: dsu clk can't change freq Solution: add sm1 dsu clk notify Verify: sm1_skt Change-Id: If3ecf1066b49c07e6af69ce342956cb0469a5f87 Signed-off-by: Shunzhou Jiang Signed-off-by: Hong Guo --- arch/arm/boot/dts/amlogic/mesonsm1.dtsi | 33 +++++++++++++++++------ arch/arm64/boot/dts/amlogic/mesonsm1.dtsi | 33 +++++++++++++++++------ 2 files changed, 50 insertions(+), 16 deletions(-) diff --git a/arch/arm/boot/dts/amlogic/mesonsm1.dtsi b/arch/arm/boot/dts/amlogic/mesonsm1.dtsi index c4db922bbd35..5e36c592be0a 100644 --- a/arch/arm/boot/dts/amlogic/mesonsm1.dtsi +++ b/arch/arm/boot/dts/amlogic/mesonsm1.dtsi @@ -58,10 +58,14 @@ cpu-idle-states = <&CPU_SLEEP_0>; clocks = <&clkc CLKID_CPU_CLK>, <&clkc CLKID_CPU_FCLK_P>, - <&clkc CLKID_SYS_PLL>; + <&clkc CLKID_SYS_PLL>, + <&clkc CLKID_DSU_CLK>, + <&clkc CLKID_DSU_PRE_CLK>; clock-names = "core_clk", "low_freq_clk_parent", - "high_freq_clk_parent"; + "high_freq_clk_parent", + "dsu_clk", + "dsu_pre_parent"; operating-points-v2 = <&cpu_opp_table0>; cpu-supply = <&vddcpu0>; voltage-tolerance = <0>; @@ -76,10 +80,14 @@ cpu-idle-states = <&CPU_SLEEP_0>; clocks = <&clkc CLKID_CPU_CLK>, <&clkc CLKID_CPU_FCLK_P>, - <&clkc CLKID_SYS_PLL>; + <&clkc CLKID_SYS_PLL>, + <&clkc CLKID_DSU_CLK>, + <&clkc CLKID_DSU_PRE_CLK>; clock-names = "core_clk", "low_freq_clk_parent", - "high_freq_clk_parent"; + "high_freq_clk_parent", + "dsu_clk", + "dsu_pre_parent"; operating-points-v2 = <&cpu_opp_table0>; cpu-supply = <&vddcpu0>; voltage-tolerance = <0>; @@ -94,10 +102,14 @@ cpu-idle-states = <&CPU_SLEEP_0>; clocks = <&clkc CLKID_CPU_CLK>, <&clkc CLKID_CPU_FCLK_P>, - <&clkc CLKID_SYS_PLL>; + <&clkc CLKID_SYS_PLL>, + <&clkc CLKID_DSU_CLK>, + <&clkc CLKID_DSU_PRE_CLK>; clock-names = "core_clk", "low_freq_clk_parent", - "high_freq_clk_parent"; + "high_freq_clk_parent", + "dsu_clk", + "dsu_pre_parent"; operating-points-v2 = <&cpu_opp_table0>; cpu-supply = <&vddcpu0>; voltage-tolerance = <0>; @@ -112,10 +124,14 @@ cpu-idle-states = <&CPU_SLEEP_0>; clocks = <&clkc CLKID_CPU_CLK>, <&clkc CLKID_CPU_FCLK_P>, - <&clkc CLKID_SYS_PLL>; + <&clkc CLKID_SYS_PLL>, + <&clkc CLKID_DSU_CLK>, + <&clkc CLKID_DSU_PRE_CLK>; clock-names = "core_clk", "low_freq_clk_parent", - "high_freq_clk_parent"; + "high_freq_clk_parent", + "dsu_clk", + "dsu_pre_parent"; operating-points-v2 = <&cpu_opp_table0>; cpu-supply = <&vddcpu0>; voltage-tolerance = <0>; @@ -762,6 +778,7 @@ compatible = "amlogic,sm1-clkc-2"; #clock-cells = <1>; reg = <0x0 0x3dc>; + own-dsu-clk; }; };/* end of hiubus*/ diff --git a/arch/arm64/boot/dts/amlogic/mesonsm1.dtsi b/arch/arm64/boot/dts/amlogic/mesonsm1.dtsi index 9fd00736aa2a..9ab39368dde2 100644 --- a/arch/arm64/boot/dts/amlogic/mesonsm1.dtsi +++ b/arch/arm64/boot/dts/amlogic/mesonsm1.dtsi @@ -58,10 +58,14 @@ cpu-idle-states = <&CPU_SLEEP_0>; clocks = <&clkc CLKID_CPU_CLK>, <&clkc CLKID_CPU_FCLK_P>, - <&clkc CLKID_SYS_PLL>; + <&clkc CLKID_SYS_PLL>, + <&clkc CLKID_DSU_CLK>, + <&clkc CLKID_DSU_PRE_CLK>; clock-names = "core_clk", "low_freq_clk_parent", - "high_freq_clk_parent"; + "high_freq_clk_parent", + "dsu_clk", + "dsu_pre_parent"; operating-points-v2 = <&cpu_opp_table0>; cpu-supply = <&vddcpu0>; voltage-tolerance = <0>; @@ -76,10 +80,14 @@ cpu-idle-states = <&CPU_SLEEP_0>; clocks = <&clkc CLKID_CPU_CLK>, <&clkc CLKID_CPU_FCLK_P>, - <&clkc CLKID_SYS_PLL>; + <&clkc CLKID_SYS_PLL>, + <&clkc CLKID_DSU_CLK>, + <&clkc CLKID_DSU_PRE_CLK>; clock-names = "core_clk", "low_freq_clk_parent", - "high_freq_clk_parent"; + "high_freq_clk_parent", + "dsu_clk", + "dsu_pre_parent"; operating-points-v2 = <&cpu_opp_table0>; cpu-supply = <&vddcpu0>; voltage-tolerance = <0>; @@ -94,10 +102,14 @@ cpu-idle-states = <&CPU_SLEEP_0>; clocks = <&clkc CLKID_CPU_CLK>, <&clkc CLKID_CPU_FCLK_P>, - <&clkc CLKID_SYS_PLL>; + <&clkc CLKID_SYS_PLL>, + <&clkc CLKID_DSU_CLK>, + <&clkc CLKID_DSU_PRE_CLK>; clock-names = "core_clk", "low_freq_clk_parent", - "high_freq_clk_parent"; + "high_freq_clk_parent", + "dsu_clk", + "dsu_pre_parent"; operating-points-v2 = <&cpu_opp_table0>; cpu-supply = <&vddcpu0>; voltage-tolerance = <0>; @@ -112,10 +124,14 @@ cpu-idle-states = <&CPU_SLEEP_0>; clocks = <&clkc CLKID_CPU_CLK>, <&clkc CLKID_CPU_FCLK_P>, - <&clkc CLKID_SYS_PLL>; + <&clkc CLKID_SYS_PLL>, + <&clkc CLKID_DSU_CLK>, + <&clkc CLKID_DSU_PRE_CLK>; clock-names = "core_clk", "low_freq_clk_parent", - "high_freq_clk_parent"; + "high_freq_clk_parent", + "dsu_clk", + "dsu_pre_parent"; operating-points-v2 = <&cpu_opp_table0>; cpu-supply = <&vddcpu0>; voltage-tolerance = <0>; @@ -762,6 +778,7 @@ compatible = "amlogic,sm1-clkc-2"; #clock-cells = <1>; reg = <0x0 0x0 0x0 0x3dc>; + own-dsu-clk; }; };/* end of hiubus*/