From 5f5f85cab71cc575f9319fc24203d3c48f65cc9b Mon Sep 17 00:00:00 2001 From: Jkand Huang Date: Wed, 27 Aug 2025 10:57:58 +0800 Subject: [PATCH 1/9] arm64: dts: rockchip: rv1126b-evb2-v10.dtsi: dsm use rn and rp pins Signed-off-by: Jkand Huang Change-Id: I63573f4cd158410d60cd522a3fbf4622f08cf3c3 --- arch/arm64/boot/dts/rockchip/rv1126b-evb2-v10.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rv1126b-evb2-v10.dtsi b/arch/arm64/boot/dts/rockchip/rv1126b-evb2-v10.dtsi index 8d3f4f1f4d2d..e5186a99fa02 100644 --- a/arch/arm64/boot/dts/rockchip/rv1126b-evb2-v10.dtsi +++ b/arch/arm64/boot/dts/rockchip/rv1126b-evb2-v10.dtsi @@ -233,6 +233,9 @@ }; &acdcdig_dsm { + pinctrl-names = "default"; + pinctrl-0 = <&dsm_aud_rn_pins + &dsm_aud_rp_pins>; pa-ctl-gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; status = "okay"; }; From 7914308c23ba800fe91a5f5f99159c7d4adbf151 Mon Sep 17 00:00:00 2001 From: Jkand Huang Date: Wed, 27 Aug 2025 11:06:15 +0800 Subject: [PATCH 2/9] arm64: dts: rockchip: rv1126b-pinctrl: set all dsm pins to pcfg_pull_down Signed-off-by: Jkand Huang Change-Id: I8251cddc014d8a6358047ea4d747a62960d8c900 --- arch/arm64/boot/dts/rockchip/rv1126b-pinctrl.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rv1126b-pinctrl.dtsi b/arch/arm64/boot/dts/rockchip/rv1126b-pinctrl.dtsi index 63010f4a4be0..f61e7435b4d4 100644 --- a/arch/arm64/boot/dts/rockchip/rv1126b-pinctrl.dtsi +++ b/arch/arm64/boot/dts/rockchip/rv1126b-pinctrl.dtsi @@ -110,28 +110,28 @@ dsm_aud_ln_pins: dsm-aud-ln-pins { rockchip,pins = /* dsm_aud_ln */ - <7 RK_PA3 4 &pcfg_pull_none>; + <7 RK_PA3 4 &pcfg_pull_down>; }; /omit-if-no-ref/ dsm_aud_lp_pins: dsm-aud-lp-pins { rockchip,pins = /* dsm_aud_lp */ - <7 RK_PA5 4 &pcfg_pull_none>; + <7 RK_PA5 4 &pcfg_pull_down>; }; /omit-if-no-ref/ dsm_aud_rn_pins: dsm-aud-rn-pins { rockchip,pins = /* dsm_aud_rn */ - <7 RK_PB0 4 &pcfg_pull_none>; + <7 RK_PB0 4 &pcfg_pull_down>; }; /omit-if-no-ref/ dsm_aud_rp_pins: dsm-aud-rp-pins { rockchip,pins = /* dsm_aud_rp */ - <7 RK_PB1 4 &pcfg_pull_none>; + <7 RK_PB1 4 &pcfg_pull_down>; }; }; From fbd92843d2515b92b69ae2ef50d1778984bd2f96 Mon Sep 17 00:00:00 2001 From: Jkand Huang Date: Wed, 27 Aug 2025 16:44:27 +0800 Subject: [PATCH 3/9] arm64: dts: rockchip: rv1126b-evb2-v10.dtsi: adjust voltage ranges for vdd_cpu and vdd_npu Signed-off-by: Jkand Huang Change-Id: Iddef11758f63ea31643898436376c2ff040d9f4d --- arch/arm64/boot/dts/rockchip/rv1126b-evb2-v10.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rv1126b-evb2-v10.dtsi b/arch/arm64/boot/dts/rockchip/rv1126b-evb2-v10.dtsi index e5186a99fa02..b50571cb946a 100644 --- a/arch/arm64/boot/dts/rockchip/rv1126b-evb2-v10.dtsi +++ b/arch/arm64/boot/dts/rockchip/rv1126b-evb2-v10.dtsi @@ -190,8 +190,8 @@ pwms = <&pwm0_8ch_0 0 25000 1>; regulator-name = "vdd_cpu"; regulator-init-microvolt = <950000>; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1100000>; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; regulator-always-on; regulator-boot-on; pwm-supply = <&vccsys_stb>; @@ -203,7 +203,7 @@ pwms = <&pwm0_8ch_1 0 25000 1>; regulator-name = "vdd_npu"; regulator-init-microvolt = <950000>; - regulator-min-microvolt = <750000>; + regulator-min-microvolt = <800000>; regulator-max-microvolt = <1100000>; regulator-always-on; regulator-boot-on; From 1825fc5818afbb6651032264102bff6d5f414800 Mon Sep 17 00:00:00 2001 From: XiaoDong Huang Date: Fri, 22 Aug 2025 09:46:27 +0800 Subject: [PATCH 4/9] rpmsg: rockchip_test: fix compile error Signed-off-by: XiaoDong Huang Change-Id: Ic9a26216e2d6494b3ce0856483ab0358250bf837 --- drivers/rpmsg/rockchip_rpmsg_test.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/rpmsg/rockchip_rpmsg_test.c b/drivers/rpmsg/rockchip_rpmsg_test.c index e8d1a0878cd4..dd01e79a41f1 100644 --- a/drivers/rpmsg/rockchip_rpmsg_test.c +++ b/drivers/rpmsg/rockchip_rpmsg_test.c @@ -47,7 +47,8 @@ static int rockchip_rpmsg_test_cb(struct rpmsg_device *rp, void *payload, ret = rpmsg_sendto(rp->ept, LINUX_TEST_MSG_2, strlen(LINUX_TEST_MSG_2), remote_ept_id); if (ret) dev_err(&rp->dev, "rpmsg_send failed: %d\n", ret); - return ret; + + return ret; } static int rockchip_rpmsg_test_probe(struct rpmsg_device *rp) From 28c7bb690ffa0bfb90e520124e1eba4d989039b0 Mon Sep 17 00:00:00 2001 From: Shawn Lin Date: Thu, 28 Aug 2025 11:22:43 +0800 Subject: [PATCH 5/9] arm64: rockchip_linux_defconfig: Enable CONFIG_NVME_HWMON Change-Id: Iabcbe619c415ae9bc4ab98982ab368f3b03c1008 Signed-off-by: Shawn Lin --- arch/arm64/configs/rockchip_linux_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/rockchip_linux_defconfig b/arch/arm64/configs/rockchip_linux_defconfig index 16dcb4cbfb59..96894fa18f4d 100644 --- a/arch/arm64/configs/rockchip_linux_defconfig +++ b/arch/arm64/configs/rockchip_linux_defconfig @@ -156,6 +156,7 @@ CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_COUNT=1 CONFIG_BLK_DEV_NVME=y +CONFIG_NVME_HWMON=y CONFIG_RK628_MISC=y CONFIG_RK628_MISC_HDMITX=y CONFIG_PCIE_FUNC_RKEP=y From 1df44e966894d258c6e4374420ffef70a8a98e77 Mon Sep 17 00:00:00 2001 From: Jon Lin Date: Thu, 28 Aug 2025 14:19:18 +0800 Subject: [PATCH 6/9] misc: rockchip: pcie-rkep: Repair accidental deletion of ioctl PCIE_EP_RESET_CTRL Fixes: 8633bf3947ac ("misc: rockchip: pcie-rkep: Support continuous buffer") Change-Id: I29bcf73f5af3d1e1a45fbb16da0b09cda9ff3f46 Signed-off-by: Jon Lin --- drivers/misc/rockchip/pcie-rkep.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/misc/rockchip/pcie-rkep.c b/drivers/misc/rockchip/pcie-rkep.c index feaa8b757636..a919ccebca2d 100644 --- a/drivers/misc/rockchip/pcie-rkep.c +++ b/drivers/misc/rockchip/pcie-rkep.c @@ -857,6 +857,7 @@ static long pcie_rkep_ioctl(struct file *file, unsigned int cmd, unsigned long a if (copy_to_user(uarg, &val, sizeof(val))) return -EFAULT; break; + case PCIE_EP_RESET_CTRL: #ifdef CONFIG_PCIEASPM_EXT dev_info(&pcie_rkep->pdev->dev, "reset controller\n"); return rockchip_dw_pcie_pm_ctrl_for_user(pcie_rkep->pdev, ROCKCHIP_PCIE_PM_CTRL_RESET); From ea8ce0984a49eda70c5c494d0bc311de6e1028d6 Mon Sep 17 00:00:00 2001 From: Wang Panzhenzhuan Date: Thu, 28 Aug 2025 11:51:26 +0800 Subject: [PATCH 7/9] media: i2c: ov08d10: fix wrong no ioctl return value Wrong noioctl return value cause rkisp get cfg failed, so fix it. Change-Id: I70e310c35a565369ea760a06f45465f78a0c321b Signed-off-by: Wang Panzhenzhuan --- drivers/media/i2c/ov08d10.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/media/i2c/ov08d10.c b/drivers/media/i2c/ov08d10.c index 6cd12e260124..6601577506d3 100644 --- a/drivers/media/i2c/ov08d10.c +++ b/drivers/media/i2c/ov08d10.c @@ -8,6 +8,7 @@ * V0.0X01.0X01 * 1. add delays in setting to fix probability reg write failed. * 2. remove duplicate global register setting. + * V0.0X01.0X02 fix wrong no ioctl return value */ //#define DEBUG #include @@ -37,7 +38,7 @@ #include #include "otp_eeprom.h" -#define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x01) +#define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x02) #ifndef V4L2_CID_DIGITAL_GAIN #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN @@ -722,7 +723,7 @@ static long ov08d10_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) ret = ov08d10_get_channel_info(ov08d10, ch_info); break; default: - ret = -ENOTTY; + ret = -ENOIOCTLCMD; break; } @@ -793,7 +794,7 @@ static long ov08d10_compat_ioctl32(struct v4l2_subdev *sd, kfree(ch_info); break; default: - ret = -ENOTTY; + ret = -ENOIOCTLCMD; break; } From 7552dcf31cb0d5ac7a2e732a54749ee1bf758452 Mon Sep 17 00:00:00 2001 From: Wang Panzhenzhuan Date: Thu, 28 Aug 2025 15:04:15 +0800 Subject: [PATCH 8/9] media: rockchip: cif: subdev-itf add update sensor info in s_power cif subdev-itf need to update sensor info in s_power, fix mipi switch case info error issue. Change-Id: I1ce93c31e4b3c1631dac4c86e30c65b6d4503624 Signed-off-by: Wang Panzhenzhuan --- drivers/media/platform/rockchip/cif/subdev-itf.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/media/platform/rockchip/cif/subdev-itf.c b/drivers/media/platform/rockchip/cif/subdev-itf.c index 5c0633c4f341..88c75c033cdd 100644 --- a/drivers/media/platform/rockchip/cif/subdev-itf.c +++ b/drivers/media/platform/rockchip/cif/subdev-itf.c @@ -1322,6 +1322,8 @@ static int sditf_s_power(struct v4l2_subdev *sd, int on) if (on && atomic_inc_return(&priv->power_cnt) > 1) return 0; + rkcif_update_sensor_info(&cif_dev->stream[0]); + if (on) rkcif_update_unite_extend_pixel(cif_dev); if (cif_dev->chip_id >= CHIP_RK3588_CIF) { From c0d2580727e9426aba8c5dd56936d8153cef134d Mon Sep 17 00:00:00 2001 From: Simon Xue Date: Tue, 19 Aug 2025 16:24:18 +0800 Subject: [PATCH 9/9] iommu/rockchip: add support pagefault fake mode Fake mode accesses memory using the DTE address as the final physical address on page fault, ignoring reads and discard writes. This resolves VOP mmu hang issues caused by page faults. Change-Id: I6b37b79a425c0341e53e0c8a786767a4b7da304e Signed-off-by: Simon Xue --- drivers/iommu/rockchip-iommu.c | 56 +++++++++++++++++++++++++++++----- 1 file changed, 48 insertions(+), 8 deletions(-) diff --git a/drivers/iommu/rockchip-iommu.c b/drivers/iommu/rockchip-iommu.c index f53b2041518e..b7c25cd59bdb 100644 --- a/drivers/iommu/rockchip-iommu.c +++ b/drivers/iommu/rockchip-iommu.c @@ -40,6 +40,9 @@ #define RK_MMU_INT_STATUS 0x20 /* IRQ status after masking */ #define RK_MMU_AUTO_GATING 0x24 +/* v3 registers */ +#define RK_MMU_PAGE_FAULT 0x44 /* Pagefault register */ + #define DTE_ADDR_DUMMY 0xCAFEBABE #define RK_MMU_POLL_PERIOD_US 100 @@ -67,6 +70,8 @@ /* RK_MMU_INT_* register fields */ #define RK_MMU_IRQ_PAGE_FAULT 0x01 /* page fault */ #define RK_MMU_IRQ_BUS_ERROR 0x02 /* bus read error */ +#define RK_MMU_IRQ_PF_FAKE_MST0 0x10000 /* page fault fake mode */ + #define RK_MMU_IRQ_MASK (RK_MMU_IRQ_PAGE_FAULT | RK_MMU_IRQ_BUS_ERROR) #define NUM_DT_ENTRIES 1024 @@ -77,6 +82,9 @@ #define DISABLE_FETCH_DTE_TIME_LIMIT BIT(31) +#define RK_MMU_PAGEFAULT_FAKE_MODE_EN BIT(24) +#define RK_MMU_PAGEFAULT_MST0_DONE BIT(0) + #define CMD_RETRY_COUNT 10 /* @@ -126,6 +134,7 @@ struct rk_iommu { struct third_iommu_ops_wrap *opt_ops; bool iommu_enabled; bool need_res_map; + bool pf_fake_mode_en; }; struct rk_iommudata { @@ -676,6 +685,7 @@ static int rk_pagefault_done(struct rk_iommu *iommu) int i; u32 int_mask; irqreturn_t ret = IRQ_NONE; + u32 val; for (i = 0; i < iommu->num_mmu; i++) { int_status = rk_iommu_read(iommu->bases[i], RK_MMU_INT_STATUS); @@ -685,7 +695,8 @@ static int rk_pagefault_done(struct rk_iommu *iommu) ret = IRQ_HANDLED; iova = rk_iommu_read(iommu->bases[i], RK_MMU_PAGE_FAULT_ADDR); - if (int_status & RK_MMU_IRQ_PAGE_FAULT) { + if ((int_status & RK_MMU_IRQ_PAGE_FAULT) || + (iommu->pf_fake_mode_en && (int_status & RK_MMU_IRQ_PF_FAKE_MST0))) { int flags; status = rk_iommu_read(iommu->bases[i], RK_MMU_STATUS); @@ -704,11 +715,13 @@ static int rk_pagefault_done(struct rk_iommu *iommu) * Ignore the return code, though, since we always zap cache * and clear the page fault anyway. */ - if (iommu->domain) - report_iommu_fault(iommu->domain, iommu->dev, iova, - status); - else + if (iommu->domain) { + if (!iommu->pf_fake_mode_en) + report_iommu_fault(iommu->domain, iommu->dev, iova, + status); + } else { dev_err(iommu->dev, "Page fault while iommu not attached to domain?\n"); + } } rk_iommu_base_command(iommu->bases[i], RK_MMU_CMD_ZAP_CACHE); @@ -726,7 +739,14 @@ static int rk_pagefault_done(struct rk_iommu *iommu) if (int_status & RK_MMU_IRQ_BUS_ERROR) dev_err(iommu->dev, "BUS_ERROR occurred at %pad\n", &iova); - if (int_status & ~RK_MMU_IRQ_MASK) + if (iommu->pf_fake_mode_en && (int_status & RK_MMU_IRQ_PF_FAKE_MST0)) { + val = rk_iommu_read(iommu->bases[i], RK_MMU_PAGE_FAULT); + val |= RK_MMU_PAGEFAULT_MST0_DONE; + rk_iommu_write(iommu->bases[i], RK_MMU_PAGE_FAULT, val); + dev_err(iommu->dev, "PF_FAKE_MST0 occurred at %pad\n", &iova); + } + + if ((int_status & ~RK_MMU_IRQ_MASK) && (!iommu->pf_fake_mode_en)) dev_err(iommu->dev, "unexpected int_status: %#08x\n", int_status); @@ -1158,6 +1178,11 @@ static int rk_iommu_enable(struct rk_iommu *iommu) struct rk_iommu_domain *rk_domain = to_rk_domain(domain); int ret, i; u32 auto_gate; + u32 page_fault; + u32 irq_mask = RK_MMU_IRQ_MASK; + + if (iommu->pf_fake_mode_en) + irq_mask |= RK_MMU_IRQ_PF_FAKE_MST0; ret = clk_bulk_enable(iommu->num_clocks, iommu->clocks); if (ret) @@ -1175,12 +1200,18 @@ static int rk_iommu_enable(struct rk_iommu *iommu) rk_iommu_write(iommu->bases[i], RK_MMU_DTE_ADDR, rk_ops->mk_dtentries(rk_domain->dt_dma)); rk_iommu_base_command(iommu->bases[i], RK_MMU_CMD_ZAP_CACHE); - rk_iommu_write(iommu->bases[i], RK_MMU_INT_MASK, RK_MMU_IRQ_MASK); + rk_iommu_write(iommu->bases[i], RK_MMU_INT_MASK, irq_mask); /* Workaround for iommu blocked, BIT(31) default to 1 */ auto_gate = rk_iommu_read(iommu->bases[i], RK_MMU_AUTO_GATING); auto_gate |= DISABLE_FETCH_DTE_TIME_LIMIT; rk_iommu_write(iommu->bases[i], RK_MMU_AUTO_GATING, auto_gate); + + if (iommu->pf_fake_mode_en) { + page_fault = rk_iommu_read(iommu->bases[i], RK_MMU_PAGE_FAULT); + page_fault |= RK_MMU_PAGEFAULT_FAKE_MODE_EN; + rk_iommu_write(iommu->bases[i], RK_MMU_PAGE_FAULT, page_fault); + } } ret = rk_iommu_enable_paging(iommu); @@ -1518,14 +1549,18 @@ void rockchip_iommu_unmask_irq(struct device *dev) { struct rk_iommu *iommu = rk_iommu_from_dev(dev); int i; + u32 irq_mask = RK_MMU_IRQ_MASK; if (!iommu) return; + if (iommu->pf_fake_mode_en) + irq_mask |= RK_MMU_IRQ_PF_FAKE_MST0; + for (i = 0; i < iommu->num_mmu; i++) { /* Need to zap tlb in case of mapping during pagefault */ rk_iommu_base_command(iommu->bases[i], RK_MMU_CMD_ZAP_CACHE); - rk_iommu_write(iommu->bases[i], RK_MMU_INT_MASK, RK_MMU_IRQ_MASK); + rk_iommu_write(iommu->bases[i], RK_MMU_INT_MASK, irq_mask); /* Leave iommu in pagefault state until mapping finished */ rk_iommu_base_command(iommu->bases[i], RK_MMU_CMD_PAGE_FAULT_DONE); } @@ -1627,6 +1662,8 @@ static int rk_iommu_probe(struct platform_device *pdev) "rockchip,reserve-map"); iommu->first_reset_disabled = device_property_read_bool(dev, "rockchip,disable-first-mmu-reset"); + iommu->pf_fake_mode_en = device_property_read_bool(dev, + "rockchip,enable-pagefault-fake-mode"); /* * iommu clocks should be present for all new devices and devicetrees * but there are older devicetrees without clocks out in the wild. @@ -1807,6 +1844,9 @@ static const struct of_device_id rk_iommu_dt_ids[] = { { .compatible = "rockchip,iommu-v2", .data = &iommu_data_ops_v2, }, + { .compatible = "rockchip,iommu-v3", + .data = &iommu_data_ops_v2, + }, { .compatible = "rockchip,rk3568-iommu", .data = &iommu_data_ops_v2, },