diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
index be9dbd221181..58387c40629f 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
@@ -695,6 +695,7 @@ struct vop2_video_port_regs {
 	struct vop_reg dclk_core_div;
 	struct vop_reg dclk_out_div;
 	struct vop_reg dclk_src_sel;
+	struct vop_reg aclk_en;
 
 	struct vop_reg splice_en;
 
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
index a8ffc825725d..9ac8bba84366 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
@@ -3274,9 +3274,11 @@ static void vop2_initial(struct drm_crtc *crtc)
 		VOP_CTRL_SET(vop2, cfg_done_en, 1);
 		/*
 		 * Disable auto gating, this is a workaround to
-		 * avoid display image shift when a window enabled.
+		 * avoid display image shift when a window enabled
+		 * on rk3566/rk3568.
 		 */
-		VOP_CTRL_SET(vop2, auto_gating_en, 0);
+		if (vop2->version == VOP_VERSION_RK3568)
+			VOP_CTRL_SET(vop2, auto_gating_en, 0);
 		/*
 		 * Register OVERLAY_LAYER_SEL and OVERLAY_PORT_SEL should take effect immediately,
 		 * than windows configuration(CLUSTER/ESMART/SMART) can take effect according the
@@ -3294,6 +3296,7 @@ static void vop2_initial(struct drm_crtc *crtc)
 		vop2->is_enabled = true;
 	}
 
+	VOP_MODULE_SET(vop2, vp, aclk_en, 1);
 	vop2_debug_irq_enable(crtc);
 
 	vop2->enable_count++;
@@ -3716,6 +3719,8 @@ static void vop2_crtc_atomic_disable(struct drm_crtc *crtc,
 
 	vop2_dsp_hold_valid_irq_disable(crtc);
 
+	VOP_MODULE_SET(vop2, vp, aclk_en, 0);
+
 	vop2_disable(crtc);
 
 	vcstate->splice_mode = false;
diff --git a/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c
index 609322d69dff..5c506507460e 100644
--- a/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c
+++ b/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c
@@ -895,6 +895,7 @@ static const struct vop2_video_port_regs rk3588_vop_vp0_regs = {
 	.splice_en = VOP_REG(RK3568_LUT_PORT_SEL, 0x1, 16),
 	.dclk_core_div = VOP_REG(RK3568_VP0_CLK_CTRL, 0x3, 0),
 	.dclk_out_div = VOP_REG(RK3568_VP0_CLK_CTRL, 0x3, 2),
+	.aclk_en = VOP_REG(RK3568_SYS_AUTO_GATING_CTRL, 0x1, 25),
 	.pre_scan_htiming = VOP_REG(RK3568_VP0_PRE_SCAN_HTIMING, 0x1fff1fff, 0),
 	.bg_dly = VOP_REG(RK3568_VP0_BG_MIX_CTRL, 0xff, 24),
 	.hpost_st_end = VOP_REG(RK3568_VP0_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
@@ -986,6 +987,7 @@ static const struct vop2_video_port_regs rk3588_vop_vp1_regs = {
 	.standby = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 31),
 	.dclk_core_div = VOP_REG(RK3568_VP1_CLK_CTRL, 0x3, 0),
 	.dclk_out_div = VOP_REG(RK3568_VP1_CLK_CTRL, 0x3, 2),
+	.aclk_en = VOP_REG(RK3568_SYS_AUTO_GATING_CTRL, 0x1, 26),
 	.pre_scan_htiming = VOP_REG(RK3568_VP1_PRE_SCAN_HTIMING, 0x1fff1fff, 0),
 	.bg_dly = VOP_REG(RK3568_VP1_BG_MIX_CTRL, 0xff, 24),
 	.hpost_st_end = VOP_REG(RK3568_VP1_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
@@ -1073,6 +1075,7 @@ static const struct vop2_video_port_regs rk3588_vop_vp2_regs = {
 	.dclk_src_sel = VOP_REG(RK3568_LUT_PORT_SEL, 0x1, 31),
 	.dclk_core_div = VOP_REG(RK3568_VP2_CLK_CTRL, 0x3, 0),
 	.dclk_out_div = VOP_REG(RK3568_VP2_CLK_CTRL, 0x3, 2),
+	.aclk_en = VOP_REG(RK3568_SYS_AUTO_GATING_CTRL, 0x1, 27),
 	.pre_scan_htiming = VOP_REG(RK3568_VP2_PRE_SCAN_HTIMING, 0x1fff1fff, 0),
 	.bg_dly = VOP_REG(RK3568_VP2_BG_MIX_CTRL, 0xff, 24),
 	.hpost_st_end = VOP_REG(RK3568_VP2_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
@@ -1130,6 +1133,7 @@ static const struct vop2_video_port_regs rk3588_vop_vp3_regs = {
 	.dclk_src_sel = VOP_REG(RK3568_LUT_PORT_SEL, 0x1, 30),
 	.dclk_core_div = VOP_REG(RK3568_VP3_CLK_CTRL, 0x3, 0),
 	.dclk_out_div = VOP_REG(RK3568_VP3_CLK_CTRL, 0x3, 2),
+	.aclk_en = VOP_REG(RK3568_SYS_AUTO_GATING_CTRL, 0x1, 28),
 	.pre_scan_htiming = VOP_REG(RK3588_VP3_PRE_SCAN_HTIMING, 0x1fff1fff, 0),
 	.bg_dly = VOP_REG(RK3588_VP3_BG_MIX_CTRL, 0xff, 24),
 	.hpost_st_end = VOP_REG(RK3588_VP3_POST_DSP_HACT_INFO, 0x1fff1fff, 0),