diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c
index ac2e9758d178..08de23d0bc36 100644
--- a/drivers/clk/rockchip/clk.c
+++ b/drivers/clk/rockchip/clk.c
@@ -222,12 +222,14 @@ static void rockchip_fractional_approximation(struct clk_hw *hw,
 				*m = 1;
 				*n = *parent_rate / rate;
 				return;
+			} else if (!(fd->flags & CLK_FRAC_DIVIDER_NO_LIMIT)) {
+				pr_warn("%s p_rate(%ld) is low than rate(%ld)*20, use integer or half-div\n",
+					clk_hw_get_name(hw),
+					*parent_rate, rate);
+				*m = 0;
+				*n = 1;
+				return;
 			}
-			pr_warn("%s p_rate(%ld) is low than rate(%ld)*20, use integer or half-div\n",
-				clk_hw_get_name(hw), *parent_rate, rate);
-			*m = 0;
-			*n = 1;
-			return;
 		}
 	}
 
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 6ce8ea3dfea1..b59dc97e1d3c 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -695,6 +695,10 @@ void clk_hw_unregister_fixed_factor(struct clk_hw *hw);
  * @lock:	register lock
  *
  * Clock with adjustable fractional divider affecting its output frequency.
+ *
+ * Flags:
+ * CLK_FRAC_DIVIDER_NO_LIMIT - not need to follow the 20 times limit on
+ *	fractional divider
  */
 struct clk_fractional_divider {
 	struct clk_hw	hw;
@@ -715,6 +719,8 @@ struct clk_fractional_divider {
 
 #define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, hw)
 
+#define CLK_FRAC_DIVIDER_NO_LIMIT		BIT(2)
+
 extern const struct clk_ops clk_fractional_divider_ops;
 struct clk *clk_register_fractional_divider(struct device *dev,
 		const char *name, const char *parent_name, unsigned long flags,