From e60c74ffd261f6d83c6a4a8b0aa948766faa4500 Mon Sep 17 00:00:00 2001 From: Brian Zhu Date: Sat, 3 Aug 2019 01:58:29 +0800 Subject: [PATCH] vpp: sr: disable more latch ctrl for SR0 [1/1] PD#TV-7673 Problem: SR0 register enabled the latch function, it will cause frame size setting out of sync when bypass sr0. Solution: Disable the latch option. Verify: Verified with X301 Change-Id: Ibfc4c5f8f695757ddd7d7d9e50e4b5be23268388 Signed-off-by: Brian Zhu --- drivers/amlogic/media/video_sink/video.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/amlogic/media/video_sink/video.c b/drivers/amlogic/media/video_sink/video.c index 266fff1f8b6d..987bba5f4e5a 100644 --- a/drivers/amlogic/media/video_sink/video.c +++ b/drivers/amlogic/media/video_sink/video.c @@ -13254,11 +13254,17 @@ static int __init video_early_init(void) /* disable latch for sr core0/1 scaler */ WRITE_VCBUS_REG_BITS( SRSHARP0_SHARP_SYNC_CTRL, 1, 0, 1); + WRITE_VCBUS_REG_BITS( + SRSHARP0_SHARP_SYNC_CTRL, 1, 8, 1); WRITE_VCBUS_REG_BITS( SRSHARP1_SHARP_SYNC_CTRL, 1, 8, 1); - } else if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12B)) + } else if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12B)) { WRITE_VCBUS_REG_BITS( SRSHARP0_SHARP_SYNC_CTRL, 1, 0, 1); + /* TODO: check if the bit8 is available */ + /* WRITE_VCBUS_REG_BITS( */ + /* SRSHARP0_SHARP_SYNC_CTRL, 1, 8, 1); */ + } return 0; }