diff --git a/Documentation/devicetree/bindings/dram/rk3368_dram_timing.txt b/Documentation/devicetree/bindings/dram/rk3368_dram_timing.txt
index 3bcde20ad952..d984c69f2086 100644
--- a/Documentation/devicetree/bindings/dram/rk3368_dram_timing.txt
+++ b/Documentation/devicetree/bindings/dram/rk3368_dram_timing.txt
@@ -50,6 +50,8 @@ Required properties:
 
 - phy_odt : define the phy odt in ohm, default value isPHY_RTT_279ohm
 
+- ddr_2t : define the uptcl CMD/CLK 2T mode, default value is ENABLE_DDR_2T.
+
 the driver strength and odt value are defined at include/dt-bindings/dram/rockchip,rk3368.h
 
 Example:
@@ -73,5 +75,6 @@ Example:
                 phy_cmd_drv = <PHY_RON_34ohm>;
                 phy_dqs_drv = <PHY_RON_34ohm>;
                 phy_odt = <PHY_RTT_279ohm>;
+		ddr_2t = <ENABLE_DDR_2T>;
         };
 };
diff --git a/arch/arm64/boot/dts/rockchip/rk3368-dram-default-timing.dtsi b/arch/arm64/boot/dts/rockchip/rk3368-dram-default-timing.dtsi
index 5e86bfa57175..10bfbebda989 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368-dram-default-timing.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3368-dram-default-timing.dtsi
@@ -61,5 +61,6 @@
 		phy_cmd_drv = <PHY_RON_34ohm>;
 		phy_dqs_drv = <PHY_RON_34ohm>;
 		phy_odt = <PHY_RTT_279ohm>;
+		ddr_2t = <ENABLE_DDR_2T>;
 	};
 };
diff --git a/include/dt-bindings/memory/rk3368-dram.h b/include/dt-bindings/memory/rk3368-dram.h
index 400f7b52a59f..c1f23d32d987 100644
--- a/include/dt-bindings/memory/rk3368-dram.h
+++ b/include/dt-bindings/memory/rk3368-dram.h
@@ -103,4 +103,7 @@
 #define PHY_RTT_80ohm		(14)
 #define PHY_RTT_74ohm		(15)
 
+#define ENABLE_DDR_2T		(1)
+#define DISABLE_DDR_2T		(0)
+
 #endif /*_DT_BINDINGS_DRAM_ROCKCHIP_RK3368_H*/