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Revert "clk: fractional-divider: check parent rate only if flag is set"

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This reverts commit d13501a2be.

This patch causes 32768Hz can't be divided from 24MHz.

Change-Id: I1e86c2b0c96be0d1a80de83d1ac5e5909becbde1
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This commit is contained in:
Finley Xiao
2019-11-25 20:04:28 +08:00
committed by Tao Huang
parent c08b33636a
commit e6dfeb296d
2 changed files with 1 additions and 4 deletions
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2
drivers/clk/clk-fractional-divider.c
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@@ -96,7 +96,7 @@ static long clk_fd_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long m, n; unsigned long m, n;
u64 ret; u64 ret;
if (!rate || (!clk_hw_can_set_rate_parent(hw) && rate >= *parent_rate)) if (!rate && rate >= *parent_rate)
return *parent_rate; return *parent_rate;
if (fd->approximation) if (fd->approximation)

3
include/linux/clk-provider.h
View File

@@ -1119,9 +1119,6 @@ int clk_hw_set_parent(struct clk_hw *hw, struct clk_hw *new_parent);
unsigned int __clk_get_enable_count(struct clk *clk); unsigned int __clk_get_enable_count(struct clk *clk);
unsigned long clk_hw_get_rate(const struct clk_hw *hw); unsigned long clk_hw_get_rate(const struct clk_hw *hw);
unsigned long clk_hw_get_flags(const struct clk_hw *hw); unsigned long clk_hw_get_flags(const struct clk_hw *hw);
#define clk_hw_can_set_rate_parent(hw) \
(clk_hw_get_flags((hw)) & CLK_SET_RATE_PARENT)
bool clk_hw_is_prepared(const struct clk_hw *hw); bool clk_hw_is_prepared(const struct clk_hw *hw);
bool clk_hw_rate_is_protected(const struct clk_hw *hw); bool clk_hw_rate_is_protected(const struct clk_hw *hw);
bool clk_hw_is_enabled(const struct clk_hw *hw); bool clk_hw_is_enabled(const struct clk_hw *hw);