dv: switch dv core3 after wm, osd_hdr and vd2_hdr [1/1]

PD#SWPL-11113

Problem:
need verify dv core3 can set after wm, osd_hdr and vd2_hdr

Solution:
switch dv core3 after wm, osd_hdr and vd2_hdr

Verify:
verified on T962e2_ab311

Change-Id: Iac5d6d113c9dc5d76dff3ef5911263a1c9dca159
Signed-off-by: Pengcheng Chen <pengcheng.chen@amlogic.com>
This commit is contained in:
Pengcheng Chen
2019-07-10 19:56:23 +08:00
committed by Jianxin Pan
parent 1a556a27d1
commit e6f679d6a5
2 changed files with 47 additions and 0 deletions

View File

@@ -268,6 +268,7 @@ static u32 vsync_count;
static bool is_osd_off;
static bool force_reset_core2;
static int core1_switch;
static int core3_switch;
module_param(vtotal_add, uint, 0664);
MODULE_PARM_DESC(vtotal_add, "\n vtotal_add\n");
module_param(vpotch, uint, 0664);
@@ -7165,6 +7166,44 @@ static ssize_t amdolby_vision_core1_switch_store(struct class *cla,
return count;
}
static ssize_t amdolby_vision_core3_switch_show(struct class *cla,
struct class_attribute *attr, char *buf)
{
return snprintf(buf, 40, "%d\n",
core3_switch);
}
static ssize_t amdolby_vision_core3_switch_store(struct class *cla,
struct class_attribute *attr,
const char *buf, size_t count)
{
size_t r;
r = kstrtoint(buf, 0, &core3_switch);
if (r != 0)
return -EINVAL;
if (is_meson_tm2_stbmode()) {
switch (core3_switch) {
case CORE3_AFTER_WM:
VSYNC_WR_DV_REG_BITS(
VPP_DOLBY_CTRL,
0, 24, 2);
break;
case CORE3_AFTER_OSD1_HDR:
VSYNC_WR_DV_REG_BITS(
VPP_DOLBY_CTRL,
1, 24, 2);
break;
case CORE3_AFTER_VD2_HDR:
VSYNC_WR_DV_REG_BITS(
VPP_DOLBY_CTRL,
2, 24, 2);
break;
}
}
return count;
}
static struct class_attribute amdolby_vision_class_attrs[] = {
__ATTR(debug, 0644,
amdolby_vision_debug_show, amdolby_vision_debug_store),
@@ -7174,6 +7213,8 @@ static struct class_attribute amdolby_vision_class_attrs[] = {
NULL, amdolby_vision_reg_store),
__ATTR(core1_switch, 0644,
amdolby_vision_core1_switch_show, amdolby_vision_core1_switch_store),
__ATTR(core3_switch, 0644,
amdolby_vision_core3_switch_show, amdolby_vision_core3_switch_store),
__ATTR_NULL
};

View File

@@ -56,6 +56,12 @@ enum core1_switch_type {
SWITCH_AFTER_DVCORE,
};
enum core3_switch_type {
CORE3_AFTER_WM = 0,
CORE3_AFTER_OSD1_HDR,
CORE3_AFTER_VD2_HDR,
};
/*! @brief Output CSC configuration.*/
# pragma pack(push, 1)
struct TgtOutCscCfg {