From e733a7a8b34b91dad35eec0d16aedc78f1a83150 Mon Sep 17 00:00:00 2001 From: Jianqun Xu Date: Fri, 18 Nov 2022 17:39:49 +0800 Subject: [PATCH] clk: rockchip: fix to SIP_V2 for rk3288 Fixes: d2b92a90eabd ("clk: rockchip: support setting ddr clock via SCPI and SIP Version 2 APIs") Signed-off-by: Jianqun Xu Change-Id: I7521443f50dbe3049fd8a08c769a74f5e364334a --- drivers/clk/rockchip/clk-rk3288.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c index 265061bb4227..f9c4678fcd73 100644 --- a/drivers/clk/rockchip/clk-rk3288.c +++ b/drivers/clk/rockchip/clk-rk3288.c @@ -339,7 +339,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { RK3288_CLKGATE_CON(0), 9, GFLAGS), COMPOSITE_DDRCLK(SCLK_DDRCLK, "sclk_ddrc", mux_ddrphy_p, 0, RK3288_CLKSEL_CON(26), 2, 1, 0, 0, - ROCKCHIP_DDRCLK_SIP), + ROCKCHIP_DDRCLK_SIP_V2), COMPOSITE_NOGATE(0, "ddrphy", mux_ddrphy_p, CLK_IGNORE_UNUSED, RK3288_CLKSEL_CON(26), 2, 1, MFLAGS, 0, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO),