From e76a8d7657b3a108a95f95aa8ba6b960a09cf642 Mon Sep 17 00:00:00 2001
From: Wu Liangqing <wlq@rock-chips.com>
Date: Mon, 14 Aug 2023 09:55:54 +0000
Subject: [PATCH] arm64: dts: rockchip: rk3588-evb3-lp5: update for v11 board

Signed-off-by: Wu Liangqing <wlq@rock-chips.com>
Change-Id: I6df2ef60133a150e658a03cfa3f7203bd871ba8a
---
 .../boot/dts/rockchip/rk3588-evb3-lp5.dtsi    | 22 +++++++++----------
 1 file changed, 11 insertions(+), 11 deletions(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb3-lp5.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-evb3-lp5.dtsi
index eca37c90b301..3603c268182d 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-evb3-lp5.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-evb3-lp5.dtsi
@@ -67,7 +67,7 @@
 	fan: pwm-fan {
 		compatible = "pwm-fan";
 		#cooling-cells = <2>;
-		pwms = <&pwm6 0 50000 0>;
+		pwms = <&pwm5 0 50000 0>;
 		cooling-levels = <0 50 100 150 200 255>;
 		rockchip,temp-trips = <
 			50000	1
@@ -815,20 +815,20 @@
 	};
 };
 
-&hdmi1 {
+&hdmi0 {
 	enable-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
 	status = "okay";
 };
 
-&hdmi1_in_vp0 {
+&hdmi0_in_vp0 {
 	status = "okay";
 };
 
-&hdmi1_sound {
+&hdmi0_sound {
 	status = "okay";
 };
 
-&hdptxphy_hdmi1 {
+&hdptxphy_hdmi0 {
 	status = "okay";
 };
 
@@ -889,9 +889,9 @@
 &i2c2 {
 	status = "okay";
 
-	usbc0: fusb302@22 {
-		compatible = "fcs,fusb302";
-		reg = <0x22>;
+	usbc0: husb311@4e {
+		compatible = "hynetek,husb311";
+		reg = <0x4e>;
 		interrupt-parent = <&gpio0>;
 		interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>;
 		pinctrl-names = "default";
@@ -1011,7 +1011,7 @@
 	};
 };
 
-&i2s6_8ch {
+&i2s5_8ch {
 	status = "okay";
 };
 
@@ -1138,8 +1138,8 @@
 	};
 };
 
-&pwm6 {
-	pinctrl-0 = <&pwm6m1_pins>;
+&pwm5 {
+	pinctrl-0 = <&pwm5m1_pins>;
 	status = "okay";
 };