From e85c2739abbecadd413ef62f8ceb8da4d81fbef8 Mon Sep 17 00:00:00 2001
From: Tony Xie <tony.xie@rock-chips.com>
Date: Sat, 7 Apr 2018 16:01:46 +0800
Subject: [PATCH] PM / devfreq: rockchip_dmc: support wait_complete.

Change-Id: Ie3f173f632068f261b84a204bbd36b26b10e1981
Signed-off-by: Tony Xie <tony.xie@rock-chips.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
---
 drivers/clk/rockchip/clk-ddr.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/clk/rockchip/clk-ddr.c b/drivers/clk/rockchip/clk-ddr.c
index 4a008f013019..426ad29f6e7d 100644
--- a/drivers/clk/rockchip/clk-ddr.c
+++ b/drivers/clk/rockchip/clk-ddr.c
@@ -22,6 +22,7 @@
 #include <linux/of.h>
 #include <linux/rockchip/rockchip_sip.h>
 #include <linux/slab.h>
+#include <soc/rockchip/rockchip_dmc.h>
 #include <soc/rockchip/rockchip_sip.h>
 #include <soc/rockchip/scpi.h>
 #include <uapi/drm/drm_mode.h>
@@ -214,6 +215,7 @@ struct share_params {
 	 * 0: never wait flag1
 	 */
 	u32 wait_flag0;
+	u32 complt_hwirq;
 	 /* if need, add parameter after */
 };
 
@@ -254,6 +256,9 @@ static int rockchip_ddrclk_sip_set_rate_v2(struct clk_hw *hw,
 	res = sip_smc_dram(SHARE_PAGE_TYPE_DDR, 0,
 			   ROCKCHIP_SIP_CONFIG_DRAM_SET_RATE);
 
+	if ((int)res.a1 == SIP_RET_SET_RATE_TIMEOUT)
+		rockchip_dmcfreq_wait_complete();
+
 	return res.a0;
 }