From e8cba68e4617facf2ae5db906a1ee42c8f5eeccc Mon Sep 17 00:00:00 2001 From: Andy Yan Date: Tue, 18 Oct 2022 16:54:53 +0800 Subject: [PATCH] drm/rockchip: vop2: no round up parent rate for low freq rockchip_rk3588_pll_round_rate will return a -EINVAL for a too low or too high freq, which will make the clk framework auto round up to a higher freq. So there is no need to do this at clk driver. static long rockchip_rk3588_pll_round_rate(struct clk_hw *hw, unsigned long drate, unsigned long *prate) { if ((drate < 37 * MHZ) || (drate > 4500 * MHZ)) return -EINVAL; else return drate; } Signed-off-by: Andy Yan Change-Id: I3f521e07b1a7639d44efbe12bdc05c4b88621a6e --- drivers/gpu/drm/rockchip/rockchip_vop2_clk.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_vop2_clk.c b/drivers/gpu/drm/rockchip/rockchip_vop2_clk.c index d381d767d726..3833923bb6a5 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop2_clk.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop2_clk.c @@ -9,8 +9,6 @@ static int cru_debug; -#define PLL_RATE_MIN 30000000 - #define cru_dbg(format, ...) do { \ if (cru_debug) \ pr_info("%s: " format, __func__, ## __VA_ARGS__); \ @@ -157,6 +155,7 @@ static long clk_virtual_round_rate(struct clk_hw *hw, unsigned long rate, vop2_clk->rate = rate; + cru_dbg("%s rate: %ld\n", clk_hw_get_name(hw), rate); return rate; } @@ -245,10 +244,6 @@ static long vop2_clk_div_round_rate(struct clk_hw *hw, unsigned long rate, if ((*prate % rate)) *prate = rate; - - /* SOC PLL can't output a too low pll freq */ - if (*prate < PLL_RATE_MIN) - *prate = rate << vop2_clk->div.width; } cru_dbg("%s rate: %ld(prate: %ld)\n", clk_hw_get_name(hw), rate, *prate);