From e984bc2a969ba8ac03e2fc3644e1ac129cfd16c2 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Sun, 14 Nov 2021 21:25:34 +0800 Subject: [PATCH] phy: rockchip: naneng-combphy: Add config option for pcie1ln-sel Add dts decode to support the pcie2x1l0 and pcie2x1l1 setting, which is in PHP_GRF_PCIESEL_CON. pcie1l0_sel Select the signal form PHY to PCIe1l0 1'b0: Select comb PHY 1'b1: Select PCIE3 PHY Usage in dts: rockchip,pcie1ln-sel-bits = <0x100 0 0 0>; Signed-off-by: Kever Yang Change-Id: I5fb177f37b23c5f3cdaadf8c103f8e6487ea6a76 --- drivers/phy/rockchip/phy-rockchip-naneng-combphy.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c index 80d398289ba8..0550d98e8252 100644 --- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c +++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c @@ -289,6 +289,7 @@ static int rockchip_combphy_parse_dt(struct device *dev, { const struct rockchip_combphy_cfg *phy_cfg = priv->cfg; int ret, mac_id; + u32 vals[4]; ret = devm_clk_bulk_get(dev, priv->num_clks, priv->clks); if (ret == -EPROBE_DEFER) @@ -322,6 +323,11 @@ static int rockchip_combphy_parse_dt(struct device *dev, param_write(priv->pipe_grf, &phy_cfg->grfcfg->pipe_sgmii_mac_sel, true); + if (!device_property_read_u32_array(dev, "rockchip,pcie1ln-sel-bits", + vals, ARRAY_SIZE(vals))) + regmap_write(priv->pipe_grf, vals[0], + (GENMASK(vals[2], vals[1]) << 16) | vals[3]); + priv->apb_rst = devm_reset_control_get_optional(dev, "combphy-apb"); if (IS_ERR(priv->apb_rst)) { ret = PTR_ERR(priv->apb_rst);