From e98e1fbdcec8cdbce54c597a79d56d5d7d4e9c89 Mon Sep 17 00:00:00 2001 From: Andrew Murray Date: Mon, 4 Nov 2019 11:12:39 -0700 Subject: [PATCH] UPSTREAM: dt-bindings: arm: coresight: Add support for coresight-loses-context-with-cpu Some coresight components, because of choices made during hardware integration, require their state to be saved and restored across CPU low power states. The software has no reliable method of detecting when save/restore is required thus let's add a binding to inform the kernel. Signed-off-by: Andrew Murray Reviewed-by: Mathieu Poirier Reviewed-by: Suzuki K Poulose Reviewed-by: Rob Herring Signed-off-by: Mathieu Poirier Link: https://lore.kernel.org/r/20191104181251.26732-3-mathieu.poirier@linaro.org Signed-off-by: Greg Kroah-Hartman (Upstream commit b7909065e8ebaffd80375d01f5d151ff59b59ce6). Bug: 140266694 Change-Id: Ie43bcbe7c80de3efef1f77900fe04595dc4904e0 Signed-off-by: Yabin Cui --- Documentation/devicetree/bindings/arm/coresight.txt | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt index 5d1ad09bafb4..410e09eca2a7 100644 --- a/Documentation/devicetree/bindings/arm/coresight.txt +++ b/Documentation/devicetree/bindings/arm/coresight.txt @@ -75,6 +75,15 @@ its hardware characteristcs. * port or ports: same as above. +* Optional properties for all components: + + * arm,coresight-loses-context-with-cpu : boolean. Indicates that the + hardware will lose register context on CPU power down (e.g. CPUIdle). + An example of where this may be needed are systems which contain a + coresight component and CPU in the same power domain. When the CPU + powers down the coresight component also powers down and loses its + context. This property is currently only used for the ETM 4.x driver. + * Optional properties for ETM/PTMs: * arm,cp14: must be present if the system accesses ETM/PTM management