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clk: rockchip: Add clock controller for the RK3568

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Add the clock tree definition for the new RK3568 SoC.

Change-Id: I9c2282938ec51ddf2dd71390b9b0cfef1f0d2735
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This commit is contained in:
Elaine Zhang
2020-07-13 16:36:35 +08:00
committed by Tao Huang
parent 472e08941e
commit e9ac850b88
4 changed files with 1829 additions and 1 deletions
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1
drivers/clk/rockchip/Makefile
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@@ -27,6 +27,7 @@ obj-$(CONFIG_CPU_RK3288) += clk-rk3288.o
obj-$(CONFIG_CPU_RK3308) += clk-rk3308.o
obj-$(CONFIG_CPU_RK3328) += clk-rk3328.o
obj-$(CONFIG_CPU_RK3368) += clk-rk3368.o
obj-$(CONFIG_CPU_RK3568) += clk-rk3568.o
obj-$(CONFIG_CPU_RK3399) += clk-rk3399.o
obj-$(CONFIG_MFD_RK618) += rk618/

25
drivers/clk/rockchip/clk-cpu.c
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@@ -165,6 +165,19 @@ static int rockchip_cpuclk_pre_rate_change(struct rockchip_cpuclk *cpuclk,
writel(HIWORD_UPDATE(alt_div, reg_data->div_core_mask,
reg_data->div_core_shift),
cpuclk->reg_base + reg_data->core_reg);
if (reg_data->core1_reg)
writel(HIWORD_UPDATE(alt_div, reg_data->div_core1_mask,
reg_data->div_core1_shift),
cpuclk->reg_base + reg_data->core1_reg);
if (reg_data->core2_reg)
writel(HIWORD_UPDATE(alt_div, reg_data->div_core2_mask,
reg_data->div_core2_shift),
cpuclk->reg_base + reg_data->core2_reg);
if (reg_data->core3_reg)
writel(HIWORD_UPDATE(alt_div, reg_data->div_core3_mask,
reg_data->div_core3_shift),
cpuclk->reg_base + reg_data->core3_reg);
}
rockchip_boost_add_core_div(cpuclk->pll_hw, alt_prate);
@@ -207,6 +220,18 @@ static int rockchip_cpuclk_post_rate_change(struct rockchip_cpuclk *cpuclk,
writel(HIWORD_UPDATE(0, reg_data->div_core_mask,
reg_data->div_core_shift),
cpuclk->reg_base + reg_data->core_reg);
if (reg_data->core1_reg)
writel(HIWORD_UPDATE(0, reg_data->div_core1_mask,
reg_data->div_core1_shift),
cpuclk->reg_base + reg_data->core1_reg);
if (reg_data->core2_reg)
writel(HIWORD_UPDATE(0, reg_data->div_core2_mask,
reg_data->div_core2_shift),
cpuclk->reg_base + reg_data->core2_reg);
if (reg_data->core3_reg)
writel(HIWORD_UPDATE(0, reg_data->div_core3_mask,
reg_data->div_core3_shift),
cpuclk->reg_base + reg_data->core3_reg);
if (ndata->old_rate > ndata->new_rate)
rockchip_cpuclk_set_dividers(cpuclk, rate);

1759
drivers/clk/rockchip/clk-rk3568.c Normal file
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File diff suppressed because it is too large Load Diff

45
drivers/clk/rockchip/clk.h
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@@ -255,6 +255,34 @@ struct clk;
#define RK3399_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x100)
#define RK3399_PMU_SOFTRST_CON(x) ((x) * 0x4 + 0x110)
#define RK3568_PLL_CON(x) RK2928_PLL_CON(x)
#define RK3568_MODE_CON0 0xc0
#define RK3568_MISC_CON0 0xc4
#define RK3568_MISC_CON1 0xc8
#define RK3568_MISC_CON2 0xcc
#define RK3568_GLB_CNT_TH 0xd0
#define RK3568_GLB_SRST_FST 0xd4
#define RK3568_GLB_SRST_SND 0xd8
#define RK3568_GLB_RST_CON 0xdc
#define RK3568_GLB_RST_ST 0xe0
#define RK3568_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
#define RK3568_CLKGATE_CON(x) ((x) * 0x4 + 0x300)
#define RK3568_SOFTRST_CON(x) ((x) * 0x4 + 0x400)
#define RK3568_SDMMC0_CON0 0x580
#define RK3568_SDMMC0_CON1 0x584
#define RK3568_SDMMC1_CON0 0x588
#define RK3568_SDMMC1_CON1 0x58c
#define RK3568_SDMMC2_CON0 0x590
#define RK3568_SDMMC2_CON1 0x594
#define RK3568_EMMC_CON0 0x598
#define RK3568_EMMC_CON1 0x59c
#define RK3568_PMU_PLL_CON(x) RK2928_PLL_CON(x)
#define RK3568_PMU_MODE_CON0 0x80
#define RK3568_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
#define RK3568_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x180)
#define RK3568_PMU_SOFTRST_CON(x) ((x) * 0x4 + 0x200)
enum rockchip_pll_type {
pll_rk3036,
pll_rk3066,
@@ -398,7 +426,7 @@ struct rockchip_cpuclk_clksel {
u32 val;
};
#define ROCKCHIP_CPUCLK_NUM_DIVIDERS 2
#define ROCKCHIP_CPUCLK_NUM_DIVIDERS 5
struct rockchip_cpuclk_rate_table {
unsigned long prate;
struct rockchip_cpuclk_clksel divs[ROCKCHIP_CPUCLK_NUM_DIVIDERS];
@@ -409,6 +437,12 @@ struct rockchip_cpuclk_rate_table {
* @core_reg: register offset of the core settings register
* @div_core_shift: core divider offset used to divide the pll value
* @div_core_mask: core divider mask
* @div_core1_shift: core1 divider offset used to divide the pll value
* @div_core1_mask: core1 divider mask
* @div_core2_shift: core2 divider offset used to divide the pll value
* @div_core2_mask: core2 divider mask
* @div_core3_shift: core3 divider offset used to divide the pll value
* @div_core3_mask: core3 divider mask
* @mux_core_alt: mux value to select alternate parent
* @mux_core_main: mux value to select main parent of core
* @mux_core_shift: offset of the core multiplexer
@@ -418,6 +452,15 @@ struct rockchip_cpuclk_reg_data {
int core_reg;
u8 div_core_shift;
u32 div_core_mask;
int core1_reg;
u8 div_core1_shift;
u32 div_core1_mask;
int core2_reg;
u8 div_core2_shift;
u32 div_core2_mask;
int core3_reg;
u8 div_core3_shift;
u32 div_core3_mask;
u8 mux_core_alt;
u8 mux_core_main;
u8 mux_core_shift;