From e9b2f6ce99f42e9f83a4aa7958e1c33bd096851c Mon Sep 17 00:00:00 2001 From: Finley Xiao Date: Thu, 6 Apr 2017 11:40:01 +0800 Subject: [PATCH] clk: rockchip: rk3288: add ddrc clock support Add a ddrc clock into clk branches, so we can do ddr frequency scaling on rk3288 platform in future. Change-Id: Ia6c93e5ce82fa30475eddf051bc9ea2512b0cc07 Signed-off-by: Finley Xiao Signed-off-by: Elaine Zhang --- drivers/clk/rockchip/clk-rk3288.c | 5 ++++- include/dt-bindings/clock/rk3288-cru.h | 1 + 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c index e72d866afb69..213192ae4054 100644 --- a/drivers/clk/rockchip/clk-rk3288.c +++ b/drivers/clk/rockchip/clk-rk3288.c @@ -329,8 +329,11 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(0), 8, GFLAGS), - GATE(0, "gpll_ddr", "gpll", 0, + GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(0), 9, GFLAGS), + COMPOSITE_DDRCLK(SCLK_DDRCLK, "sclk_ddrc", mux_ddrphy_p, 0, + RK3288_CLKSEL_CON(26), 2, 1, 0, 0, + ROCKCHIP_DDRCLK_SIP), COMPOSITE_NOGATE(0, "ddrphy", mux_ddrphy_p, CLK_IGNORE_UNUSED, RK3288_CLKSEL_CON(26), 2, 1, MFLAGS, 0, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO), diff --git a/include/dt-bindings/clock/rk3288-cru.h b/include/dt-bindings/clock/rk3288-cru.h index 9d8c9c76f640..0680ef855ef6 100644 --- a/include/dt-bindings/clock/rk3288-cru.h +++ b/include/dt-bindings/clock/rk3288-cru.h @@ -80,6 +80,7 @@ #define SCLK_CRYPTO 125 #define SCLK_MIPIDSI_24M 126 #define SCLK_VIP_OUT 127 +#define SCLK_DDRCLK 128 #define SCLK_MAC 151 #define SCLK_MACREF_OUT 152