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drm/rockchip: drv: fix the dclk calculation of mcu interface

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dclk = htotal * vtotal * frame-rate * cycles-per-pixel * pix-total

Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: I6b78463dc8290f562cfe44040d6b6030d652213d
This commit is contained in:
Damon Ding
2023-07-18 10:34:49 +08:00
parent 8405687e7c
commit ea3b81ee34
4 changed files with 36 additions and 17 deletions
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24
drivers/gpu/drm/rockchip/rockchip_drm_drv.c
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@@ -200,6 +200,30 @@ uint32_t rockchip_drm_get_bpp(const struct drm_format_info *info)
} }
EXPORT_SYMBOL(rockchip_drm_get_bpp); EXPORT_SYMBOL(rockchip_drm_get_bpp);
uint32_t rockchip_drm_get_cycles_per_pixel(uint32_t bus_format)
{
switch (bus_format) {
case MEDIA_BUS_FMT_RGB565_1X16:
case MEDIA_BUS_FMT_RGB666_1X18:
case MEDIA_BUS_FMT_RGB888_1X24:
case MEDIA_BUS_FMT_RGB666_1X24_CPADHI:
return 1;
case MEDIA_BUS_FMT_RGB565_2X8_LE:
case MEDIA_BUS_FMT_BGR565_2X8_LE:
return 2;
case MEDIA_BUS_FMT_RGB666_3X6:
case MEDIA_BUS_FMT_RGB888_3X8:
case MEDIA_BUS_FMT_BGR888_3X8:
return 3;
case MEDIA_BUS_FMT_RGB888_DUMMY_4X8:
case MEDIA_BUS_FMT_BGR888_DUMMY_4X8:
return 4;
default:
return 1;
}
}
EXPORT_SYMBOL(rockchip_drm_get_cycles_per_pixel);
/** /**
* rockchip_drm_of_find_possible_crtcs - find the possible CRTCs for an active * rockchip_drm_of_find_possible_crtcs - find the possible CRTCs for an active
* encoder port * encoder port

1
drivers/gpu/drm/rockchip/rockchip_drm_drv.h
View File

@@ -567,6 +567,7 @@ int rockchip_drm_endpoint_is_subdriver(struct device_node *ep);
uint32_t rockchip_drm_of_find_possible_crtcs(struct drm_device *dev, uint32_t rockchip_drm_of_find_possible_crtcs(struct drm_device *dev,
struct device_node *port); struct device_node *port);
uint32_t rockchip_drm_get_bpp(const struct drm_format_info *info); uint32_t rockchip_drm_get_bpp(const struct drm_format_info *info);
uint32_t rockchip_drm_get_cycles_per_pixel(uint32_t bus_format);
int rockchip_drm_get_yuv422_format(struct drm_connector *connector, int rockchip_drm_get_yuv422_format(struct drm_connector *connector,
struct edid *edid); struct edid *edid);
int rockchip_drm_parse_cea_ext(struct rockchip_drm_dsc_cap *dsc_cap, int rockchip_drm_parse_cea_ext(struct rockchip_drm_dsc_cap *dsc_cap,

8
drivers/gpu/drm/rockchip/rockchip_drm_vop.c
View File

@@ -3080,8 +3080,8 @@ static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
{ {
struct vop *vop = to_vop(crtc); struct vop *vop = to_vop(crtc);
const struct vop_data *vop_data = vop->data; const struct vop_data *vop_data = vop->data;
struct rockchip_crtc_state *s = struct drm_crtc_state *new_crtc_state = container_of(mode, struct drm_crtc_state, mode);
to_rockchip_crtc_state(crtc->state); struct rockchip_crtc_state *s = to_rockchip_crtc_state(new_crtc_state);
if (mode->hdisplay > vop_data->max_output.width) if (mode->hdisplay > vop_data->max_output.width)
return false; return false;
@@ -3097,6 +3097,10 @@ static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
s->output_if & VOP_OUTPUT_IF_BT656)) s->output_if & VOP_OUTPUT_IF_BT656))
adj_mode->crtc_clock *= 2; adj_mode->crtc_clock *= 2;
if (vop->mcu_timing.mcu_pix_total)
adj_mode->crtc_clock *= rockchip_drm_get_cycles_per_pixel(s->bus_format) *
(vop->mcu_timing.mcu_pix_total + 1);
adj_mode->crtc_clock = adj_mode->crtc_clock =
DIV_ROUND_UP(clk_round_rate(vop->dclk, adj_mode->crtc_clock * 1000), DIV_ROUND_UP(clk_round_rate(vop->dclk, adj_mode->crtc_clock * 1000),
1000); 1000);

20
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
View File

@@ -6832,12 +6832,9 @@ static bool vop2_crtc_mode_fixup(struct drm_crtc *crtc,
if (mode->flags & DRM_MODE_FLAG_DBLCLK || vcstate->output_if & VOP_OUTPUT_IF_BT656) if (mode->flags & DRM_MODE_FLAG_DBLCLK || vcstate->output_if & VOP_OUTPUT_IF_BT656)
adj_mode->crtc_clock *= 2; adj_mode->crtc_clock *= 2;
if (vp->mcu_timing.mcu_pix_total) { if (vp->mcu_timing.mcu_pix_total)
if (vcstate->output_mode == ROCKCHIP_OUT_MODE_S888) adj_mode->crtc_clock *= rockchip_drm_get_cycles_per_pixel(vcstate->bus_format) *
adj_mode->crtc_clock *= 3; (vp->mcu_timing.mcu_pix_total + 1);
else if (vcstate->output_mode == ROCKCHIP_OUT_MODE_S888_DUMMY)
adj_mode->crtc_clock *= 4;
}
drm_connector_list_iter_begin(crtc->dev, &conn_iter); drm_connector_list_iter_begin(crtc->dev, &conn_iter);
drm_for_each_connector_iter(connector, &conn_iter) { drm_for_each_connector_iter(connector, &conn_iter) {
@@ -7693,14 +7690,6 @@ static void vop3_setup_pipe_dly(struct vop2_video_port *vp, const struct vop2_zp
} }
} }
static int vop2_get_vrefresh(struct vop2_video_port *vp, const struct drm_display_mode *mode)
{
if (vp->mcu_timing.mcu_pix_total)
return drm_mode_vrefresh(mode) / vp->mcu_timing.mcu_pix_total;
else
return drm_mode_vrefresh(mode);
}
static void vop2_crtc_atomic_enable(struct drm_crtc *crtc, struct drm_crtc_state *old_state) static void vop2_crtc_atomic_enable(struct drm_crtc *crtc, struct drm_crtc_state *old_state)
{ {
struct vop2_video_port *vp = to_vop2_video_port(crtc); struct vop2_video_port *vp = to_vop2_video_port(crtc);
@@ -7746,7 +7735,8 @@ static void vop2_crtc_atomic_enable(struct drm_crtc *crtc, struct drm_crtc_state
vop2_lock(vop2); vop2_lock(vop2);
DRM_DEV_INFO(vop2->dev, "Update mode to %dx%d%s%d, type: %d(if:%x, flag:0x%x) for vp%d dclk: %d\n", DRM_DEV_INFO(vop2->dev, "Update mode to %dx%d%s%d, type: %d(if:%x, flag:0x%x) for vp%d dclk: %d\n",
hdisplay, adjusted_mode->vdisplay, interlaced ? "i" : "p", hdisplay, adjusted_mode->vdisplay, interlaced ? "i" : "p",
vop2_get_vrefresh(vp, adjusted_mode), vcstate->output_type, vcstate->output_if, vcstate->output_flags, drm_mode_vrefresh(adjusted_mode),
vcstate->output_type, vcstate->output_if, vcstate->output_flags,
vp->id, adjusted_mode->crtc_clock * 1000); vp->id, adjusted_mode->crtc_clock * 1000);
if (adjusted_mode->hdisplay > VOP2_MAX_VP_OUTPUT_WIDTH) { if (adjusted_mode->hdisplay > VOP2_MAX_VP_OUTPUT_WIDTH) {