vdin: vdin add dolby vision de-scramble & scramble

PD#SWPL-14888

Problem:
New feature, dolby source vdin have de-scramble,
scrable function

Solution:
add feature for dv de scramble function

Verify:
tm2 ab301

Change-Id: Ib7c10fcf53232c84411ae366618b2ddcd9948527
Signed-off-by: Yong Qin <yong.qin@amlogic.com>
This commit is contained in:
Yong Qin
2019-10-12 17:40:14 +08:00
committed by Tao Zeng
parent a9e5f5eefd
commit ea5ce3ec54
7 changed files with 137 additions and 25 deletions

View File

@@ -64,6 +64,7 @@ static unsigned int rgb_info_b;
static int vdin_det_idle_wait = 100;
static unsigned int delay_line_num;
static bool invert_top_bot;
unsigned int vdin0_afbce_debug_force;
#ifdef DEBUG_SUPPORT
module_param(rgb_info_enable, bool, 0644);
@@ -2832,6 +2833,7 @@ void vdin_set_dolby_ll_tunnel(struct vdin_dev_s *devp)
&& (devp->dv.low_latency)
&& (devp->prop.color_format == TVIN_YUV422)) {
offset = devp->addr_offset;
/*channel map*/
wr_bits(offset, VDIN_COM_CTRL0, vdin_data_bus_0,
COMP0_OUT_SWT_BIT, COMP0_OUT_SWT_WID);
wr_bits(offset, VDIN_COM_CTRL0, vdin_data_bus_1,
@@ -2839,7 +2841,13 @@ void vdin_set_dolby_ll_tunnel(struct vdin_dev_s *devp)
wr_bits(offset, VDIN_COM_CTRL0, vdin_data_bus_2,
COMP2_OUT_SWT_BIT, COMP2_OUT_SWT_WID);
sm_ops = devp->frontend->sm_ops;
/*hdmi rs call back, 422 tunnel to 444*/
sm_ops->hdmi_dv_config(true, devp->frontend);
/*vdin de tunnel and tunnel for vdin scaling*/
if (devp->dv.de_scramble)
vdin_dolby_desc_sc_enable(devp, 1);
else
vdin_dolby_desc_sc_enable(devp, 0);
}
}
@@ -2858,6 +2866,7 @@ static void vdin_delay_line(unsigned short num, unsigned int offset)
void vdin_set_default_regmap(unsigned int offset)
{
unsigned int def_canvas_id;
/* unsigned int offset = devp->addr_offset; */
/* [ 31] mpeg.en = 0 ***sub_module.enable*** */
@@ -2986,7 +2995,6 @@ void vdin_set_default_regmap(unsigned int offset)
wr(offset, VDIN_LFIFO_CTRL, 0x00000f00);
else if (is_meson_tm2_cpu()) {
wr(offset, VDIN_LFIFO_CTRL, 0xc0020f00);
/*set vdin0 out to mif0 normal begin*/
if (offset == 0) {
wr_bits(0, VDIN_TOP_DOUBLE_CTRL, WR_SEL_DIS,
@@ -2995,7 +3003,6 @@ void vdin_set_default_regmap(unsigned int offset)
MIF0_OUT_SEL_BIT, VDIN_REORDER_SEL_WID);
}
/*set vdin0 out to mif0 normal end*/
wr(offset, VDIN_HDR2_MATRIXI_EN_CTRL, 0);
} else
wr(offset, VDIN_LFIFO_CTRL, 0x00000780);
@@ -3649,6 +3656,10 @@ void vdin_set_hvscale(struct vdin_dev_s *devp)
{
unsigned int offset = devp->addr_offset;
unsigned int vshrk_mode = 0;
/*backup current h v size*/
devp->h_active_org = devp->h_active;
devp->v_active_org = devp->v_active;
if ((devp->prop.scaling4w < devp->h_active) &&
(devp->prop.scaling4w > 0)) {
if (devp->prehsc_en && (devp->prop.scaling4w <=
@@ -4273,7 +4284,67 @@ void vdin_dobly_mdata_write_en(unsigned int offset, unsigned int en)
}
}
unsigned int vdin0_afbce_debug_force;
/*
* set dv de-scramble scramble, and this function
* need call after vdin_set_hvscale if vdin scaling down
* enable
* parm: devp
* on:1 off:0
*/
void vdin_dolby_desc_sc_enable(struct vdin_dev_s *devp,
unsigned int onoff)
{
unsigned int data;
unsigned int offset = 0;
if (is_meson_tm2_cpu()) {
if (onoff) {
/*for test dolby vision de-scramble to scramble*/
/*dolby vision scramble locate in small path*/
data = (1 << 31) | /*Linebuffer soft reset enable*/
(1 << 30) | /*Frame reset enable*/
(1 << 18) | /*Discard data enable*/
(0 << 17) | /*
* Vdin ch0 output enable :
* normal size
*/
(0 << 16) | /*Pps_path_sel*/
(0xf00); /*lfifo_buf_size*/
wr(offset, VDIN_LFIFO_CTRL, data);
wr(offset, VDIN_LFIFO_CTRL, 0xc0040f00);
/*switch vdin 0 wr mif to small*/
data = (5 << 24) | /*Vdin1_interrupt mask*/
(5 << 20) | /*Vdin0_interrupt mask*/
(0 << 16) | /*Done flag clear*/
(0 << 12) | /*vdin2 wr mif sel*/
(3 << 8) | /*vdin1 wr mif sel*/
(2 << 4) | /*vdin0 wr mif sel*/
(0);/*afbce sel*/
wr(0, VDIN_TOP_DOUBLE_CTRL, data);
wr(0, VDIN_TOP_DOUBLE_CTRL, 0x5500320);
wr(0, VDIN_DSC_DETUNNEL_SEL, 0x2c2d0);
wr(0, VDIN_DSC_TUNNEL_SEL, 0x3d11);
/*de-scramble h size in*/
wr_bits(0, VDIN_CFMT_W, devp->h_active_org / 2, 0, 13);
wr_bits(0, VDIN_CFMT_W, devp->h_active_org, 16, 13);
/**/
wr_bits(0, VDIN_DSC_HSIZE, devp->h_active_org, 0, 13);
wr_bits(0, VDIN_DSC_HSIZE, devp->h_active_org, 16, 13);
/*scaler out size*/
wr_bits(0, VDIN_SCB_CTRL1, devp->v_active, 0, 13);
wr_bits(0, VDIN_SCB_CTRL1, devp->h_active, 16, 13);
/*enable descramble & scramble*/
wr_bits(0, VDIN_VSHRK_CTRL, 0x3, 28, 2);
} else {
/*enable descramble & scramble*/
wr_bits(0, VDIN_VSHRK_CTRL, 0x0, 28, 2);
}
}
}
int vdin_event_cb(int type, void *data, void *op_arg)
{
unsigned long flags;

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@@ -189,6 +189,8 @@ extern void vdin_prob_matrix_sel(unsigned int offset,
unsigned int sel, struct vdin_dev_s *devp);
void vdin_change_matrix(unsigned int offset,
unsigned int matrix_csc);
void vdin_dolby_desc_sc_enable(struct vdin_dev_s *devp,
unsigned int onoff);
#endif

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@@ -1515,6 +1515,7 @@ static ssize_t vdin_attr_store(struct device *dev,
unsigned int time_start, time_end, time_delta;
long val = 0;
unsigned int temp;
unsigned int mode = 0, flag = 0;
if (!buf)
return len;
@@ -1885,6 +1886,13 @@ start_chk:
(reg+offset), rd(offset, reg));
}
pr_info("vdin%d regs end----\n", devp->index);
pr_info("vdin descramble scramble----start\n");
for (reg = VDIN_DSC_CTRL; reg <= VDIN_DSC_TUNNEL_SEL;
reg++) {
pr_info("0x%04x = 0x%08x\n",
(reg), R_VCBUS(reg));
}
pr_info("vdin descramble scramble----end\n");
if (devp->afbce_flag & VDIN_AFBCE_EN) {
pr_info("vdin%d afbce regs start----\n", devp->index);
for (reg = AFBCE_ENABLE; reg <= AFBCE_MMU_RMIF_RO_STAT;
@@ -2264,8 +2272,6 @@ start_chk:
pr_info("vdin_afbce_flag: 0x%x\n", devp->afbce_flag);
}
} else if (!strcmp(parm[0], "afbce_mode")) {
unsigned int mode = 0, flag = 0;
if (parm[2] != NULL) {
if ((kstrtouint(parm[1], 10, &mode) == 0) &&
(kstrtouint(parm[2], 10, &flag) == 0)) {
@@ -2313,6 +2319,15 @@ start_chk:
if (kstrtouint(parm[1], 10, &temp) == 0)
vdin_change_matrix(0, temp);
}
} else if (!strcmp(parm[0], "scramble")) {
if (parm[1]) {
if (kstrtouint(parm[1], 10, &mode) == 0) {
pr_info("dv scramble %d\n", mode);
dv_de_scramble = mode;
devp->dv.de_scramble = mode;
vdin_dolby_desc_sc_enable(devp, mode);
}
}
} else {
pr_info("unknown command\n");
}

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@@ -152,6 +152,10 @@ unsigned int vdin_drop_cnt;
module_param(vdin_drop_cnt, uint, 0664);
MODULE_PARM_DESC(vdin_drop_cnt, "vdin_drop_cnt");
unsigned int dv_de_scramble;
module_param(dv_de_scramble, uint, 0664);
MODULE_PARM_DESC(dv_de_scramble, "dv_de_scramble");
static unsigned int panel_reverse;
@@ -630,6 +634,7 @@ void vdin_start_dec(struct vdin_dev_s *devp)
if (vdin_dbg_en)
pr_info("vdin start dec dv input config\n");
} else {
/*disable dv mdata write*/
vdin_dobly_mdata_write_en(devp->addr_offset, 0);
}
#endif
@@ -651,6 +656,7 @@ void vdin_start_dec(struct vdin_dev_s *devp)
vdin_hw_enable(devp->addr_offset);
vdin_set_all_regs(devp);
devp->dv.de_scramble = dv_de_scramble;
vdin_set_dolby_ll_tunnel(devp);
vdin_write_mif_or_afbce_init(devp);
if (!(devp->parm.flag & TVIN_PARM_FLAG_CAP) &&
@@ -776,6 +782,8 @@ void vdin_stop_dec(struct vdin_dev_s *devp)
#endif
vf_unreg_provider(&devp->vprov);
devp->dv.dv_config = 0;
devp->dv.de_scramble = 0;
vdin_dolby_desc_sc_enable(devp, 0);
if (devp->afbce_mode == 1) {
vdin_afbce_hw_disable();
@@ -2968,7 +2976,13 @@ static long vdin_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
pr_err("[vdin.%d] idx %d RECOVERY error\n",
devp->index, recov_idx);
break;
case TVIN_IOC_S_DV_DESCRAMBLE:
if (copy_from_user(&idx, argp, sizeof(idx)))
return -EFAULT;
dv_de_scramble = idx;
devp->dv.de_scramble = dv_de_scramble;
vdin_dolby_desc_sc_enable(devp, dv_de_scramble);
break;
default:
ret = -ENOIOCTLCMD;
/* pr_info("%s %d is not supported command\n", __func__, cmd); */

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@@ -48,7 +48,7 @@
/* Ref.2019/04/25: tl1 vdin0 afbce dynamically switch support,
* vpp also should support this function
*/
#define VDIN_VER "Ref.2019/10/11:Fix coverify error"
#define VDIN_VER "ver:2019-1030: add dv descramble scramble feature"
/*the counter of vdin*/
#define VDIN_MAX_DEVS 2
@@ -271,6 +271,7 @@ struct vdin_dv_s {
unsigned int dv_mem_alloced;
struct tvin_dv_vsif_s dv_vsif;/*dolby vsi info*/
bool low_latency;
bool de_scramble;
};
struct vdin_afbce_s {
@@ -338,6 +339,8 @@ struct vdin_dev_s {
unsigned int h_active;
unsigned int v_active;
unsigned int h_active_org;/*vdin scaler in*/
unsigned int v_active_org;/*vdin scaler in*/
unsigned int canvas_h;
unsigned int canvas_w;
unsigned int canvas_active_w;
@@ -492,6 +495,7 @@ extern unsigned int max_ignore_frame_cnt;
extern unsigned int skip_frame_debug;
extern unsigned int vdin_drop_cnt;
extern unsigned int vdin0_afbce_debug_force;
extern unsigned int dv_de_scramble;
extern struct vframe_provider_s *vf_get_provider_by_name(
const char *provider_name);

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@@ -641,21 +641,18 @@
/* Bit 5:0, vdi9_asfifo_cnt */
#define VDIN_COM_STATUS3 ((0x1273))/* + 0xd0100000) */
/* dolby vdin regs */
#define VDIN_DOLBY_DSC_CTRL0 0x1275
/*((0x1275 << 2) + 0xff900000)*/
#define VDIN_DOLBY_DSC_CTRL1 0x1276
#define VDIN_DOLBY_DSC_CTRL2 0x1277
#define VDIN_DOLBY_DSC_CTRL3 0x1278
#define VDIN_DOLBY_AXI_CTRL0 0x1279
#define VDIN_DOLBY_AXI_CTRL1 0x127a
#define VDIN_DOLBY_AXI_CTRL2 0x127b
#define VDIN_DOLBY_AXI_CTRL3 0x127c
#define VDIN_DOLBY_DSC_STATUS0 0x127d
#define VDIN_DOLBY_DSC_STATUS1 0x127e
#define VDIN_DOLBY_DSC_STATUS2 0x127f
#define VDIN_DOLBY_DSC_STATUS3 0x121d
#define VDIN_DOLBY_DSC_CTRL0 0x1275
#define VDIN_DOLBY_DSC_CTRL1 0x1276
#define VDIN_DOLBY_DSC_CTRL2 0x1277
#define VDIN_DOLBY_DSC_CTRL3 0x1278
#define VDIN_DOLBY_AXI_CTRL0 0x1279
#define VDIN_DOLBY_AXI_CTRL1 0x127a
#define VDIN_DOLBY_AXI_CTRL2 0x127b
#define VDIN_DOLBY_AXI_CTRL3 0x127c
#define VDIN_DOLBY_DSC_STATUS0 0x127d
#define VDIN_DOLBY_DSC_STATUS1 0x127e
#define VDIN_DOLBY_DSC_STATUS2 0x127f
#define VDIN_DOLBY_DSC_STATUS3 0x121d
/*g12a new add begin*/
#define VDIN_HDR2_CTRL 0x1280
@@ -760,10 +757,18 @@
/*tm2 new add end*/
/* #define VDIN_SCALE_COEF_IDX 0x1200 */
/* #define VDIN_SCALE_COEF 0x1201 */
/* dolby de-scramble scramble register */
#define VDIN_DSC_CTRL 0x12d0
#define VDIN_CFMT_CTRL 0x12d1
#define VDIN_CFMT_W 0x12d2
#define VDIN_SCB_CTRL0 0x12d3
#define VDIN_SCB_CTRL1 0x12d4
#define VDIN_DSC_HSIZE 0x12d5
#define VDIN_DSC_DETUNNEL_SEL 0x12d6
#define VDIN_DSC_TUNNEL_SEL 0x12d7
#define VDIN_TOP_MISC 0x410d
/* #define VDIN_COM_CTRL0 0x1202 */
/* used by other modules,indicates that MPEG input.
*0: mpeg source to NR directly,
*1: mpeg source pass through here

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@@ -499,6 +499,7 @@ struct tvafe_pin_mux_s {
#define TVIN_IOC_S_VDIN_V4L2START _IOW(_TM_T, 0x25, struct vdin_v4l2_param_s)
#define TVIN_IOC_S_VDIN_V4L2STOP _IO(_TM_T, 0x26)
#define TVIN_IOC_S_AFE_SONWCFG _IOW(_TM_T, 0x27, unsigned int)
#define TVIN_IOC_S_DV_DESCRAMBLE _IOW(_TM_T, 0x28, unsigned int)
/*
*function defined applied for other driver