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RDMA/bnxt_re: Fix a bug while setting up Level-2 PBL pages
[ Upstream commit 7988bdbbb85ac85a847baf09879edcd0f70521dc ]
Avoid memory corruption while setting up Level-2 PBL pages for the non MR
resources when num_pages > 256K.
There will be a single PDE page address (contiguous pages in the case of >
PAGE_SIZE), but, current logic assumes multiple pages, leading to invalid
memory access after 256K PBL entries in the PDE.
Fixes: 0c4dcd6028 ("RDMA/bnxt_re: Refactor hardware queue memory allocation")
Link: https://patch.msgid.link/r/1728373302-19530-10-git-send-email-selvin.xavier@broadcom.com
Signed-off-by: Bhargava Chenna Marreddy <bhargava.marreddy@broadcom.com>
Signed-off-by: Selvin Xavier <selvin.xavier@broadcom.com>
Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
committed by
Greg Kroah-Hartman
parent
ff80a98104
commit
ea701c1849
@@ -257,22 +257,9 @@ int bnxt_qplib_alloc_init_hwq(struct bnxt_qplib_hwq *hwq,
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dst_virt_ptr =
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dst_virt_ptr =
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(dma_addr_t **)hwq->pbl[PBL_LVL_0].pg_arr;
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(dma_addr_t **)hwq->pbl[PBL_LVL_0].pg_arr;
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src_phys_ptr = hwq->pbl[PBL_LVL_1].pg_map_arr;
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src_phys_ptr = hwq->pbl[PBL_LVL_1].pg_map_arr;
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if (hwq_attr->type == HWQ_TYPE_MR) {
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for (i = 0; i < hwq->pbl[PBL_LVL_1].pg_count; i++)
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/* For MR it is expected that we supply only 1 contigous
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dst_virt_ptr[0][i] = src_phys_ptr[i] | flag;
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* page i.e only 1 entry in the PDL that will contain
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* all the PBLs for the user supplied memory region
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*/
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for (i = 0; i < hwq->pbl[PBL_LVL_1].pg_count;
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i++)
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dst_virt_ptr[0][i] = src_phys_ptr[i] |
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flag;
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} else {
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for (i = 0; i < hwq->pbl[PBL_LVL_1].pg_count;
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i++)
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dst_virt_ptr[PTR_PG(i)][PTR_IDX(i)] =
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src_phys_ptr[i] |
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PTU_PDE_VALID;
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}
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/* Alloc or init PTEs */
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/* Alloc or init PTEs */
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rc = __alloc_pbl(res, &hwq->pbl[PBL_LVL_2],
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rc = __alloc_pbl(res, &hwq->pbl[PBL_LVL_2],
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hwq_attr->sginfo);
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hwq_attr->sginfo);
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