diff --git a/drivers/clk/rockchip/clk-rk1808.c b/drivers/clk/rockchip/clk-rk1808.c
index 47604a6b346c..fc2b58330b40 100644
--- a/drivers/clk/rockchip/clk-rk1808.c
+++ b/drivers/clk/rockchip/clk-rk1808.c
@@ -603,12 +603,12 @@ static struct rockchip_clk_branch rk1808_clk_branches[] __initdata = {
 	GATE(HCLK_SFC, "hclk_sfc", "hclk_mmc_sfc", 0,
 			RK1808_CLKGATE_CON(9), 13, GFLAGS),
 
-	MUX(0, "clk_sdio_src", mux_gpll_cpll_npll_24m_p, 0,
-			RK1808_CLKSEL_CON(22), 14, 2, MFLAGS),
-	COMPOSITE_NOMUX(SCLK_SDIO_DIV, "clk_sdio_div", "clk_sdio_src", CLK_IGNORE_UNUSED,
-			RK1808_CLKSEL_CON(22), 0, 8, DFLAGS,
+	COMPOSITE(SCLK_SDIO_DIV, "clk_sdio_div", mux_gpll_cpll_npll_24m_p, CLK_IGNORE_UNUSED,
+			RK1808_CLKSEL_CON(22), 14, 2, MFLAGS, 0, 8, DFLAGS,
 			RK1808_CLKGATE_CON(9), 1, GFLAGS),
-	COMPOSITE_NOMUX(SCLK_SDIO_DIV50, "clk_sdio_div50", "clk_sdio_src", CLK_IGNORE_UNUSED,
+	COMPOSITE_DIV_OFFSET(SCLK_SDIO_DIV50, "clk_sdio_div50",
+			mux_gpll_cpll_npll_24m_p, CLK_IGNORE_UNUSED,
+			RK1808_CLKSEL_CON(22), 14, 2, MFLAGS,
 			RK1808_CLKSEL_CON(23), 0, 8, DFLAGS,
 			RK1808_CLKGATE_CON(9), 2, GFLAGS),
 	COMPOSITE_NODIV(SCLK_SDIO, "clk_sdio", mux_sdio_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
@@ -618,12 +618,12 @@ static struct rockchip_clk_branch rk1808_clk_branches[] __initdata = {
 	MMC(SCLK_SDIO_DRV,     "sdio_drv",    "clk_sdio", RK1808_SDIO_CON0, 1),
 	MMC(SCLK_SDIO_SAMPLE,  "sdio_sample", "clk_sdio", RK1808_SDIO_CON1, 1),
 
-	MUX(0, "clk_emmc_src", mux_gpll_cpll_npll_24m_p, 0,
-			RK1808_CLKSEL_CON(24), 14, 2, MFLAGS),
-	COMPOSITE_NOMUX(SCLK_EMMC_DIV, "clk_emmc_div", "clk_emmc_src", CLK_IGNORE_UNUSED,
-			RK1808_CLKSEL_CON(24), 0, 8, DFLAGS,
+	COMPOSITE(SCLK_EMMC_DIV, "clk_emmc_div",
+			mux_gpll_cpll_npll_24m_p, CLK_IGNORE_UNUSED,
+			RK1808_CLKSEL_CON(24), 14, 2, MFLAGS, 0, 8, DFLAGS,
 			RK1808_CLKGATE_CON(9), 4, GFLAGS),
-	COMPOSITE_NOMUX(SCLK_EMMC_DIV50, "clk_emmc_div50", "clk_emmc_src", CLK_IGNORE_UNUSED,
+	COMPOSITE_DIV_OFFSET(SCLK_EMMC_DIV50, "clk_emmc_div50", mux_gpll_cpll_npll_24m_p, CLK_IGNORE_UNUSED,
+			RK1808_CLKSEL_CON(24), 14, 2, MFLAGS,
 			RK1808_CLKSEL_CON(25), 0, 8, DFLAGS,
 			RK1808_CLKGATE_CON(9), 5, GFLAGS),
 	COMPOSITE_NODIV(SCLK_EMMC, "clk_emmc", mux_emmc_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
@@ -632,12 +632,12 @@ static struct rockchip_clk_branch rk1808_clk_branches[] __initdata = {
 	MMC(SCLK_EMMC_DRV,     "emmc_drv",    "clk_emmc", RK1808_EMMC_CON0, 1),
 	MMC(SCLK_EMMC_SAMPLE,  "emmc_sample", "clk_emmc", RK1808_EMMC_CON1, 1),
 
-	MUX(0, "clk_sdmmc_src", mux_gpll_cpll_npll_24m_p, 0,
-			RK1808_CLKSEL_CON(20), 14, 2, MFLAGS),
-	COMPOSITE_NOMUX(SCLK_SDMMC_DIV, "clk_sdmmc_div", "clk_sdmmc_src", CLK_IGNORE_UNUSED,
-			RK1808_CLKSEL_CON(20), 0, 8, DFLAGS,
+	COMPOSITE(SCLK_SDMMC_DIV, "clk_sdmmc_div", mux_gpll_cpll_npll_24m_p, CLK_IGNORE_UNUSED,
+			RK1808_CLKSEL_CON(20), 14, 2, MFLAGS, 0, 8, DFLAGS,
 			RK1808_CLKGATE_CON(9), 7, GFLAGS),
-	COMPOSITE_NOMUX(SCLK_SDMMC_DIV50, "clk_sdmmc_div50", "clk_sdmmc_src", CLK_IGNORE_UNUSED,
+	COMPOSITE_DIV_OFFSET(SCLK_SDMMC_DIV50, "clk_sdmmc_div50",
+			mux_gpll_cpll_npll_24m_p, CLK_IGNORE_UNUSED,
+			RK1808_CLKSEL_CON(20), 14, 2, MFLAGS,
 			RK1808_CLKSEL_CON(21), 0, 8, DFLAGS,
 			RK1808_CLKGATE_CON(9), 8, GFLAGS),
 	COMPOSITE_NODIV(SCLK_SDMMC, "clk_sdmmc", mux_sdmmc_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,