From ead9f87f94fc31c9997dc373c7506d4587ccfee7 Mon Sep 17 00:00:00 2001
From: Cai YiWei <cyw@rock-chips.com>
Date: Tue, 8 Mar 2022 17:20:22 +0800
Subject: [PATCH] ARM: dts: rockchip: add isp nodes for rv1106

Change-Id: I93e20fccdd7269efac7e22eb7a83bbfea3ea22c3
Signed-off-by: Cai YiWei <cyw@rock-chips.com>
---
 arch/arm/boot/dts/rv1106.dtsi | 38 +++++++++++++++++++++++++++++++++++
 1 file changed, 38 insertions(+)

diff --git a/arch/arm/boot/dts/rv1106.dtsi b/arch/arm/boot/dts/rv1106.dtsi
index ed09b4b7647f..5ec7a280b5df 100644
--- a/arch/arm/boot/dts/rv1106.dtsi
+++ b/arch/arm/boot/dts/rv1106.dtsi
@@ -95,6 +95,30 @@
 		};
 	};
 
+	rkisp_vir0: rkisp-vir0 {
+		compatible = "rockchip,rkisp-vir";
+		rockchip,hw = <&rkisp>;
+		status = "disabled";
+	};
+
+	rkisp_vir1: rkisp-vir1 {
+		compatible = "rockchip,rkisp-vir";
+		rockchip,hw = <&rkisp>;
+		status = "disabled";
+	};
+
+	rkisp_vir2: rkisp-vir2 {
+		compatible = "rockchip,rkisp-vir";
+		rockchip,hw = <&rkisp>;
+		status = "disabled";
+	};
+
+	rkisp_vir3: rkisp-vir3 {
+		compatible = "rockchip,rkisp-vir";
+		rockchip,hw = <&rkisp>;
+		status = "disabled";
+	};
+
 	timer {
 		compatible = "arm,armv7-timer";
 		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
@@ -755,6 +779,20 @@
 		status = "disabled";
 	};
 
+	rkisp: rkisp@ffa00000 {
+		compatible = "rockchip,rv1106-rkisp";
+		reg = <0xffa00000 0x7f00>;
+		interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "isp_irq", "mi_irq", "mipi_irq";
+		clocks = <&cru ACLK_ISP3P2>, <&cru HCLK_ISP3P2>,
+			 <&cru CLK_CORE_ISP3P2>, <&cru ISP0CLK_VICAP>;
+		clock-names = "aclk_isp", "hclk_isp",
+			      "clk_isp_core", "clk_isp_core_vicap";
+		status = "disabled";
+	};
+
 	gmac: ethernet@ffa80000 {
 		compatible = "rockchip,rv1106-gmac", "snps,dwmac-4.20a";
 		reg = <0xffa80000 010000>;