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deinterlace: vpp: change mc update flow [1/1]

Browse Source 
PD#SWPL-14142

Problem:
display abnormal after play 1 hour.
this is because rdma can't been called in two thread.
mc update bit in hw timer, this causes pps's register
to be set incorrectly.

Solution:
call mc update function in video.c

Verify:
txlx

Change-Id: I750aa5c242a1077691f82c3b2361ee46b3202313
Signed-off-by: Jihong Sui <jihong.sui@amlogic.com>
This commit is contained in:
Jihong Sui
2019-09-16 19:35:32 +08:00
committed by Tao Zeng
parent 55ba0d911f
commit eba8feda63
6 changed files with 20 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
drivers/amlogic/media/deinterlace/deinterlace.c
View File

@@ -462,6 +462,7 @@ static int lDI_POST_WR_REG_BITS(u32 adr, u32 val, u32 start, u32 len)
static const struct di_ext_ops di_ext = {
.di_post_reg_rd = lDI_POST_REG_RD,
.di_post_wr_reg_bits = lDI_POST_WR_REG_BITS,
.post_update_mc = di_patch_post_update_mc,
};
#endif
@@ -7320,7 +7321,7 @@ static enum hrtimer_restart di_pre_hrtimer_func(struct hrtimer *timer)
if (!di_pre_stru.bypass_flag)
di_pre_trigger_work(&di_pre_stru);
hrtimer_forward_now(&di_pre_hrtimer, ms_to_ktime(10));
di_patch_post_update_mc();
/*di_patch_post_update_mc();*/
return HRTIMER_RESTART;
}

7
drivers/amlogic/media/di_local/di_local.c
View File

@@ -127,6 +127,13 @@ int DI_POST_WR_REG_BITS(u32 adr, u32 val, u32 start, u32 len)
}
EXPORT_SYMBOL(DI_POST_WR_REG_BITS);
void DI_POST_UPDATE_MC(void)
{
if (dil_api && dil_api->post_update_mc)
dil_api->post_update_mc();
}
EXPORT_SYMBOL(DI_POST_UPDATE_MC);
/***************************************
* reserved mem for di *
**************************************/

1
drivers/amlogic/media/di_local/di_local.h
View File

@@ -21,6 +21,7 @@
struct di_ext_ops {
unsigned int (*di_post_reg_rd)(unsigned int addr);
int (*di_post_wr_reg_bits)(u32 adr, u32 val, u32 start, u32 len);
void (*post_update_mc)(void);
};
#endif /*__DI_LOCAL_H__*/

1
drivers/amlogic/media/di_multi/di_api.c
View File

@@ -26,6 +26,7 @@
static const struct di_ext_ops di_ext = {
.di_post_reg_rd = l_DI_POST_REG_RD,
.di_post_wr_reg_bits = l_DI_POST_WR_REG_BITS,
.post_update_mc = NULL,
};
void dim_attach_to_local(void)

7
drivers/amlogic/media/video_sink/video.c
View File

@@ -6681,6 +6681,7 @@ static irqreturn_t vsync_isr_in(int irq, void *dev_id)
struct vframe_s *cur_dispbuf_back = cur_dispbuf;
static struct vframe_s *pause_vf;
int force_flush = 0;
bool di_post_process_done = false;
static u32 interrupt_count;
int ret = 0;
u32 next_afbc_request = atomic_read(&gAfbc_request);
@@ -8290,9 +8291,15 @@ SET_FILTER:
24) | (frame_par_di_set << 16),
zoom_end_x_lines, zoom_start_y_lines,
zoom_end_y_lines, cur_dispbuf);
di_post_process_done = true;
}
exit:
if (legacy_vpp &&
!di_post_process_done &&
(DI_POST_REG_RD(DI_POST_CTRL) & 0x100))
DI_POST_UPDATE_MC();
#if defined(PTS_LOGGING) || defined(PTS_TRACE_DEBUG)
pts_trace++;
#endif

2
include/linux/amlogic/media/video_sink/video.h
View File

@@ -247,5 +247,7 @@ void set_video_angle(u32 s_value);
u32 get_video_angle(void);
extern unsigned int DI_POST_REG_RD(unsigned int addr);
extern int DI_POST_WR_REG_BITS(u32 adr, u32 val, u32 start, u32 len);
void DI_POST_UPDATE_MC(void);
extern void videosync_pcrscr_update(s32 inc, u32 base);
#endif /* VIDEO_H */