From ebe7656936e35d592ac8e4a6ccfb29bc778d1b38 Mon Sep 17 00:00:00 2001 From: Shawn Lin Date: Mon, 22 Nov 2021 15:50:15 +0800 Subject: [PATCH] mmc: sdhci-of-dwcmshc: Add more clk management for runtime PM core clk should be alive for DLL to work properlly, but we can set it to 24MHz to save power. And other bulk clks can be closed too. Signed-off-by: Shawn Lin Change-Id: I402ae1e8ca8cd00f33e8bbdeaa89e41546f954ff --- drivers/mmc/host/sdhci-of-dwcmshc.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-of-dwcmshc.c index 65ac03066cc0..8aa303ecc21c 100644 --- a/drivers/mmc/host/sdhci-of-dwcmshc.c +++ b/drivers/mmc/host/sdhci-of-dwcmshc.c @@ -73,6 +73,7 @@ struct dwcmshc_priv { struct clk *bus_clk; + u32 cclk_rate; /* Rockchip specified optional clocks */ struct clk_bulk_data rockchip_clks[ROCKCHIP_MAX_CLKS]; @@ -532,6 +533,9 @@ static int dwcmshc_runtime_suspend(struct device *dev) priv->actual_clk = host->mmc->actual_clock; sdhci_set_clock(host, 0); + priv->cclk_rate = clk_get_rate(pltfm_host->clk); + clk_set_rate(pltfm_host->clk, 24000000); + clk_bulk_disable_unprepare(ROCKCHIP_MAX_CLKS, priv->rockchip_clks); return 0; } @@ -541,10 +545,13 @@ static int dwcmshc_runtime_resume(struct device *dev) struct sdhci_host *host = dev_get_drvdata(dev); struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); + int ret = 0; + clk_set_rate(pltfm_host->clk, priv->cclk_rate); sdhci_set_clock(host, priv->actual_clk); + ret = clk_bulk_prepare_enable(ROCKCHIP_MAX_CLKS, priv->rockchip_clks); - return 0; + return ret; } #endif