From ec130295af58df1b710329be7afa0831e4d8947b Mon Sep 17 00:00:00 2001 From: Guochun Huang Date: Tue, 7 Nov 2023 07:41:12 +0000 Subject: [PATCH] drm/rockchip: dsi2: sys_clk and pixel_clk should not be zero Change-Id: I8a92a1d12093b3562566349707c7ee0308e7d01c Signed-off-by: Guochun Huang --- drivers/gpu/drm/rockchip/dw-mipi-dsi2-rockchip.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi2-rockchip.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi2-rockchip.c index 05f38f14c0b8..cae0353ec3e8 100644 --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi2-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi2-rockchip.c @@ -629,6 +629,9 @@ static void dw_mipi_dsi2_phy_ratio_cfg(struct dw_mipi_dsi2 *dsi2) pixel_clk = mode->crtc_clock * MSEC_PER_SEC; ipi_clk = pixel_clk / 4; + if (!sys_clk || !ipi_clk) + return; + tmp = DIV_ROUND_CLOSEST_ULL(phy_hsclk << 16, ipi_clk); regmap_write(dsi2->regmap, DSI2_PHY_IPI_RATIO_MAN_CFG, PHY_IPI_RATIO(tmp));