From ec50666d2117669813e7d006179074b922029f94 Mon Sep 17 00:00:00 2001 From: Guochun Huang Date: Wed, 19 Jul 2023 01:41:08 +0000 Subject: [PATCH] phy: rockchip: mipi-dcphy: fix HSTX_CLK_SEL config set HSTX_CLK_SEL 1`b1 when cphy lane rate under 500Msps, while set HSTX_CLK_SEL 1`b1 when dphy lane rate under 1500Mbps Change-Id: Ic42ce385c1952febe0327594231f6bffb2543c5e Signed-off-by: Guochun Huang --- drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c b/drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c index 8e9e71923791..48b570d5a4a7 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c @@ -1466,9 +1466,9 @@ static void samsung_mipi_cphy_timing_init(struct samsung_mipi_dcphy *samsung) /* * Divide-by-2 Clock from Serial Clock. Use this when data rate is under - * 1500Mbps, otherwise divide-by-16 Clock from Serial Clock + * 500Msps, otherwise divide-by-16 Clock from Serial Clock */ - if (lane_hs_rate < 1500) + if (lane_hs_rate < 500) val = HSTX_CLK_SEL; val |= T_LPX(timing->lpx);