diff --git a/MAINTAINERS b/MAINTAINERS index 92cf8294d0b7..cf718b525c17 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14280,6 +14280,7 @@ AMLOGIC G12A clk tree for media/gpu M: Qiufang Dai F: drivers/amlogic/clk/g12a/g12a_clk_gpu.c F: drivers/amlogic/clk/g12a/g12a_clk_media.c +F: drivers/amlogic/clk/g12a/g12a_clk_misc.c AMLOGIC VOUT_SERVE M: Evoke Zhang diff --git a/drivers/amlogic/clk/clkc.h b/drivers/amlogic/clk/clkc.h index 3add60dffca3..a3663bc258f6 100644 --- a/drivers/amlogic/clk/clkc.h +++ b/drivers/amlogic/clk/clkc.h @@ -243,5 +243,6 @@ void meson_init_gpu(void); void meson_g12a_sdemmc_init(void); void meson_g12a_media_init(void); void meson_g12a_gpu_init(void); +void meson_g12a_misc_init(void); #endif /* __CLKC_H */ diff --git a/drivers/amlogic/clk/g12a/Makefile b/drivers/amlogic/clk/g12a/Makefile index 6d8a9b86943e..ae81de7468e6 100644 --- a/drivers/amlogic/clk/g12a/Makefile +++ b/drivers/amlogic/clk/g12a/Makefile @@ -3,7 +3,4 @@ # obj-$(CONFIG_AMLOGIC_GX_CLK) += g12a.o g12a_clk-pll.o g12a_clk_sdemmc.o g12a_clk-mpll.o \ - g12a_clk_media.o g12a_clk_gpu.o - -# g12a_ao.o\ - g12a_clk_sdemmc.o g12a_clk_media.o g12a_clk_misc.o + g12a_clk_media.o g12a_clk_gpu.o g12a_clk_misc.o diff --git a/drivers/amlogic/clk/g12a/g12a.c b/drivers/amlogic/clk/g12a/g12a.c index a965f6eef894..0d8b5942bdc7 100644 --- a/drivers/amlogic/clk/g12a/g12a.c +++ b/drivers/amlogic/clk/g12a/g12a.c @@ -619,7 +619,6 @@ static struct clk_gate g12a_clk81 = { }, }; - /* Everything Else (EE) domain gates */ static MESON_GATE(g12a_ddr, HHI_GCLK_MPEG0, 0); static MESON_GATE(g12a_dos, HHI_GCLK_MPEG0, 1); @@ -646,7 +645,7 @@ static MESON_GATE(g12a_acodec, HHI_GCLK_MPEG0, 28); static MESON_GATE(g12a_audio, HHI_GCLK_MPEG1, 0); static MESON_GATE(g12a_eth_core, HHI_GCLK_MPEG1, 3); -static MESON_GATE(g12a_u_stp_top, HHI_GCLK_MPEG1, 4); +static MESON_GATE(g12a_demux, HHI_GCLK_MPEG1, 4); static MESON_GATE(g12a_aififo, HHI_GCLK_MPEG1, 11); static MESON_GATE(g12a_adc, HHI_GCLK_MPEG1, 13); static MESON_GATE(g12a_uart1, HHI_GCLK_MPEG1, 16); @@ -669,6 +668,26 @@ static MESON_GATE(g12a_uart2, HHI_GCLK_MPEG2, 15); static MESON_GATE(g12a_vpu_intr, HHI_GCLK_MPEG2, 25); static MESON_GATE(g12a_gic, HHI_GCLK_MPEG2, 30); +static MESON_GATE(g12a_vclk2_venci0, HHI_GCLK_OTHER, 1); +static MESON_GATE(g12a_vclk2_venci1, HHI_GCLK_OTHER, 2); +static MESON_GATE(g12a_vclk2_vencp0, HHI_GCLK_OTHER, 3); +static MESON_GATE(g12a_vclk2_vencp1, HHI_GCLK_OTHER, 4); +static MESON_GATE(g12a_vclk2_venct0, HHI_GCLK_OTHER, 5); +static MESON_GATE(g12a_vclk2_venct1, HHI_GCLK_OTHER, 6); +static MESON_GATE(g12a_vclk2_other, HHI_GCLK_OTHER, 7); +static MESON_GATE(g12a_vclk2_enci, HHI_GCLK_OTHER, 8); +static MESON_GATE(g12a_vclk2_encp, HHI_GCLK_OTHER, 9); +static MESON_GATE(g12a_dac_clk, HHI_GCLK_OTHER, 10); +static MESON_GATE(g12a_aoclk_gate, HHI_GCLK_OTHER, 14); +static MESON_GATE(g12a_iec958_gate, HHI_GCLK_OTHER, 16); +static MESON_GATE(g12a_enc480p, HHI_GCLK_OTHER, 20); +static MESON_GATE(g12a_rng1, HHI_GCLK_OTHER, 21); +static MESON_GATE(g12a_vclk2_enct, HHI_GCLK_OTHER, 22); +static MESON_GATE(g12a_vclk2_encl, HHI_GCLK_OTHER, 23); +static MESON_GATE(g12a_vclk2_venclmmc, HHI_GCLK_OTHER, 24); +static MESON_GATE(g12a_vclk2_vencl, HHI_GCLK_OTHER, 25); +static MESON_GATE(g12a_vclk2_other1, HHI_GCLK_OTHER, 26); + /* Always On (AO) domain gates */ #if 0 static MESON_GATE(g12a_ao_media_cpu, HHI_GCLK_AO, 0); @@ -724,14 +743,14 @@ static struct clk_hw *g12a_clk_hws[] = { [CLKID_ACODEC] = &g12a_acodec.hw, [CLKID_AUDIO] = &g12a_audio.hw, [CLKID_ETH_CORE] = &g12a_eth_core.hw, - [CLKID_U_STP_TOP] = &g12a_u_stp_top.hw, + [CLKID_DEMUX] = &g12a_demux.hw, [CLKID_AIFIFO] = &g12a_aififo.hw, [CLKID_ADC] = &g12a_adc.hw, [CLKID_UART1] = &g12a_uart1.hw, [CLKID_G2D] = &g12a_g2d.hw, [CLKID_RESET] = &g12a_reset.hw, [CLKID_PCIE_COMB] = &g12a_pcie_comb.hw, - [CLKID_PARSER] = &g12a_parser.hw, + [CLKID_DOS_PARSER] = &g12a_parser.hw, [CLKID_USB_GENERAL] = &g12a_usb_general.hw, [CLKID_PCIE_PHY] = &g12a_pcie_phy.hw, [CLKID_AHB_ARB0] = &g12a_ahb_arb0.hw, @@ -745,6 +764,25 @@ static struct clk_hw *g12a_clk_hws[] = { [CLKID_UART2] = &g12a_uart2.hw, [CLKID_VPU_INTR] = &g12a_vpu_intr.hw, [CLKID_GIC] = &g12a_gic.hw, + [CLKID_VCLK2_VENCI0] = &g12a_vclk2_venci0.hw, + [CLKID_VCLK2_VENCI1] = &g12a_vclk2_venci1.hw, + [CLKID_VCLK2_VENCP0] = &g12a_vclk2_vencp0.hw, + [CLKID_VCLK2_VENCP1] = &g12a_vclk2_vencp1.hw, + [CLKID_VCLK2_VENCT0] = &g12a_vclk2_venct0.hw, + [CLKID_VCLK2_VENCT1] = &g12a_vclk2_venct1.hw, + [CLKID_VCLK2_OTHER] = &g12a_vclk2_other.hw, + [CLKID_VCLK2_ENCI] = &g12a_vclk2_enci.hw, + [CLKID_VCLK2_ENCP] = &g12a_vclk2_encp.hw, + [CLKID_DAC_CLK] = &g12a_dac_clk.hw, + [CLKID_AOCLK_GATE] = &g12a_aoclk_gate.hw, + [CLKID_IEC958_GATE] = &g12a_iec958_gate.hw, + [CLKID_ENC480P] = &g12a_enc480p.hw, + [CLKID_RNG1] = &g12a_rng1.hw, + [CLKID_VCLK2_ENCT] = &g12a_vclk2_enct.hw, + [CLKID_VCLK2_ENCL] = &g12a_vclk2_encl.hw, + [CLKID_VCLK2_VENCLMMC] = &g12a_vclk2_venclmmc.hw, + [CLKID_VCLK2_VENCL] = &g12a_vclk2_vencl.hw, + [CLKID_VCLK2_OTHER1] = &g12a_vclk2_other1.hw, #if 0 [CLKID_AO_MEDIA_CPU] = &g12a_ao_media_cpu.hw, @@ -807,7 +845,7 @@ static struct clk_gate *g12a_clk_gates[] = { &g12a_acodec, &g12a_audio, &g12a_eth_core, - &g12a_u_stp_top, + &g12a_demux, &g12a_aififo, &g12a_adc, &g12a_uart1, @@ -828,6 +866,25 @@ static struct clk_gate *g12a_clk_gates[] = { &g12a_uart2, &g12a_vpu_intr, &g12a_gic, + &g12a_vclk2_venci0, + &g12a_vclk2_venci1, + &g12a_vclk2_vencp0, + &g12a_vclk2_vencp1, + &g12a_vclk2_venct0, + &g12a_vclk2_venct1, + &g12a_vclk2_other, + &g12a_vclk2_enci, + &g12a_vclk2_encp, + &g12a_dac_clk, + &g12a_aoclk_gate, + &g12a_iec958_gate, + &g12a_enc480p, + &g12a_rng1, + &g12a_vclk2_enct, + &g12a_vclk2_encl, + &g12a_vclk2_venclmmc, + &g12a_vclk2_vencl, + &g12a_vclk2_other1, #if 0 &g12a_ao_media_cpu, &g12a_ao_ahb_sram, @@ -914,7 +971,7 @@ static void __init g12a_clkc_init(struct device_node *np) meson_g12a_sdemmc_init(); meson_g12a_gpu_init(); meson_g12a_media_init(); - /*g12a_amlogic_init_misc();*/ + meson_g12a_misc_init(); pr_debug("%s: register all clk ok!", __func__); /* diff --git a/drivers/amlogic/clk/g12a/g12a.h b/drivers/amlogic/clk/g12a/g12a.h index c692f4f15050..b4c9bff81d32 100644 --- a/drivers/amlogic/clk/g12a/g12a.h +++ b/drivers/amlogic/clk/g12a/g12a.h @@ -42,18 +42,20 @@ #define HHI_GCLK_MPEG0 0x140 /* 0x50 offset in data sheet */ #define HHI_GCLK_MPEG1 0x144 /* 0x51 offset in data sheet */ #define HHI_GCLK_MPEG2 0x148 /* 0x52 offset in data sheet */ +#define HHI_GCLK_OTHER 0x150 /* 0x54 offset in data sheet */ + #if 0 #define HHI_GCLK_AO 0x154 /* 0x55 offset in data sheet */ #define HHI_VID_CLK_DIV 0x164 /* 0x59 offset in data sheet */ #define HHI_SPICC_HCLK_CNTL 0x168 /* 0x5a offset in data sheet */ #endif -#define HHI_MPEG_CLK_CNTL 0x174 /* 0x5d offset in data sheet */ -#define HHI_AUD_CLK_CNTL 0x178 /* 0x5e offset in data sheet */ -#define HHI_VID_CLK_CNTL 0x17c /* 0x5f offset in data sheet */ -//#define HHI_AUD_CLK_CNTL2 0x190 /* 0x64 offset in data sheet */ -#define HHI_VID_CLK_CNTL2 0x194 /* 0x65 offset in data sheet */ -#define HHI_SYS_CPU_CLK_CNTL0 0x19c /* 0x67 offset in data sheet */ +#define HHI_MPEG_CLK_CNTL 0x174 /* 0x5d offset in data sheet */ +#define HHI_AUD_CLK_CNTL 0x178 /* 0x5e offset in data sheet */ +#define HHI_VID_CLK_CNTL 0x17c /* 0x5f offset in data sheet */ +#define HHI_TS_CLK_CNTL 0x190 /* 0x64 offset in data sheet */ +#define HHI_VID_CLK_CNTL2 0x194 /* 0x65 offset in data sheet */ +#define HHI_SYS_CPU_CLK_CNTL0 0x19c /* 0x67 offset in data sheet */ #define HHI_MALI_CLK_CNTL 0x1b0 /* 0x6c offset in data sheet */ #define HHI_VPU_CLK_CNTL 0x1bC /* 0x6f offset in data sheet */ diff --git a/drivers/amlogic/clk/g12a/g12a_clk_media.c b/drivers/amlogic/clk/g12a/g12a_clk_media.c index 34b182705e2e..09a49a1709ab 100644 --- a/drivers/amlogic/clk/g12a/g12a_clk_media.c +++ b/drivers/amlogic/clk/g12a/g12a_clk_media.c @@ -80,6 +80,336 @@ static struct clk_hw *dsi_meas_clk_hws[] = { }; #endif +const char *g12a_dec_parent_names[] = { "fclk_div2p5", "fclk_div3", + "fclk_div4", "fclk_div5", "fclk_div7", "hifi_pll", "gp0_pll", "xtal"}; + +/* cts_vdec_clk */ +static struct clk_mux vdec_p0_mux = { + .reg = (void *)HHI_VDEC_CLK_CNTL, + .mask = 0x7, + .shift = 9, + .lock = &clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "vdec_p0_mux", + .ops = &clk_mux_ops, + .parent_names = g12a_dec_parent_names, + .num_parents = 8, + .flags = CLK_GET_RATE_NOCACHE, + }, +}; + +static struct clk_divider vdec_p0_div = { + .reg = (void *)HHI_VDEC_CLK_CNTL, + .shift = 0, + .width = 7, + .lock = &clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "vdec_p0_div", + .ops = &clk_divider_ops, + .parent_names = (const char *[]){ "vdec_p0_mux" }, + .num_parents = 1, + .flags = CLK_GET_RATE_NOCACHE, + }, +}; + +static struct clk_gate vdec_p0_gate = { + .reg = (void *)HHI_VDEC_CLK_CNTL, + .bit_idx = 8, + .lock = &clk_lock, + .hw.init = &(struct clk_init_data) { + .name = "vdec_p0_gate", + .ops = &clk_gate_ops, + .parent_names = (const char *[]){ "vdec_p0_div" }, + .num_parents = 1, + .flags = CLK_GET_RATE_NOCACHE, + }, +}; + +static struct clk_mux vdec_p1_mux = { + .reg = (void *)HHI_VDEC3_CLK_CNTL, + .mask = 0x7, + .shift = 9, + .lock = &clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "vdec_p1_mux", + .ops = &clk_mux_ops, + .parent_names = g12a_dec_parent_names, + .num_parents = 8, + .flags = CLK_GET_RATE_NOCACHE, + }, +}; + +static struct clk_divider vdec_p1_div = { + .reg = (void *)HHI_VDEC3_CLK_CNTL, + .shift = 0, + .width = 7, + .lock = &clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "vdec_p1_div", + .ops = &clk_divider_ops, + .parent_names = (const char *[]){ "vdec_p1_mux" }, + .num_parents = 1, + .flags = CLK_GET_RATE_NOCACHE, + }, +}; + +static struct clk_gate vdec_p1_gate = { + .reg = (void *)HHI_VDEC3_CLK_CNTL, + .bit_idx = 8, + .lock = &clk_lock, + .hw.init = &(struct clk_init_data) { + .name = "vdec_p1_gate", + .ops = &clk_gate_ops, + .parent_names = (const char *[]){ "vdec_p1_div" }, + .num_parents = 1, + .flags = CLK_GET_RATE_NOCACHE, + }, +}; + +static struct clk_mux vdec_mux = { + .reg = (void *)HHI_VDEC3_CLK_CNTL, + .mask = 0x1, + .shift = 15, + .lock = &clk_lock, + .flags = CLK_PARENT_ALTERNATE, + .hw.init = &(struct clk_init_data){ + .name = "vdec_mux", + .ops = &meson_clk_mux_ops, + .parent_names = (const char *[]){ "vdec_p0_composite", + "vdec_p1_composite"}, + .num_parents = 2, + .flags = CLK_GET_RATE_NOCACHE, + }, +}; + +static struct clk_hw *vdec_clk_hws[] = { + [CLKID_VDEC_P0_MUX - CLKID_VDEC_P0_MUX] = &vdec_p0_mux.hw, + [CLKID_VDEC_P0_DIV - CLKID_VDEC_P0_MUX] = &vdec_p0_div.hw, + [CLKID_VDEC_P0_GATE - CLKID_VDEC_P0_MUX] = &vdec_p0_gate.hw, + [CLKID_VDEC_P1_MUX - CLKID_VDEC_P0_MUX] = &vdec_p1_mux.hw, + [CLKID_VDEC_P1_DIV - CLKID_VDEC_P0_MUX] = &vdec_p1_div.hw, + [CLKID_VDEC_P1_GATE - CLKID_VDEC_P0_MUX] = &vdec_p1_gate.hw, + [CLKID_VDEC_MUX - CLKID_VDEC_P0_MUX] = &vdec_mux.hw, +}; + +/* cts_hcodec_clk */ +static struct clk_mux hcodec_p0_mux = { + .reg = (void *)HHI_VDEC_CLK_CNTL, + .mask = 0x7, + .shift = 25, + .lock = &clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "hcodec_p0_mux", + .ops = &clk_mux_ops, + .parent_names = g12a_dec_parent_names, + .num_parents = 8, + .flags = CLK_GET_RATE_NOCACHE, + }, +}; + +static struct clk_divider hcodec_p0_div = { + .reg = (void *)HHI_VDEC_CLK_CNTL, + .shift = 16, + .width = 7, + .lock = &clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "hcodec_p0_div", + .ops = &clk_divider_ops, + .parent_names = (const char *[]){ "hcodec_p0_mux" }, + .num_parents = 1, + .flags = CLK_GET_RATE_NOCACHE, + }, +}; + +static struct clk_gate hcodec_p0_gate = { + .reg = (void *)HHI_VDEC_CLK_CNTL, + .bit_idx = 24, + .lock = &clk_lock, + .hw.init = &(struct clk_init_data) { + .name = "hcodec_p0_gate", + .ops = &clk_gate_ops, + .parent_names = (const char *[]){ "hcodec_p0_div" }, + .num_parents = 1, + .flags = CLK_GET_RATE_NOCACHE, + }, +}; + +static struct clk_mux hcodec_p1_mux = { + .reg = (void *)HHI_VDEC3_CLK_CNTL, + .mask = 0x7, + .shift = 25, + .lock = &clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "hcodec_p1_mux", + .ops = &clk_mux_ops, + .parent_names = g12a_dec_parent_names, + .num_parents = 8, + .flags = CLK_GET_RATE_NOCACHE, + }, +}; + +static struct clk_divider hcodec_p1_div = { + .reg = (void *)HHI_VDEC3_CLK_CNTL, + .shift = 16, + .width = 7, + .lock = &clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "hcodec_p1_div", + .ops = &clk_divider_ops, + .parent_names = (const char *[]){ "hcodec_p1_mux" }, + .num_parents = 1, + .flags = CLK_GET_RATE_NOCACHE, + }, +}; + +static struct clk_gate hcodec_p1_gate = { + .reg = (void *)HHI_VDEC3_CLK_CNTL, + .bit_idx = 24, + .lock = &clk_lock, + .hw.init = &(struct clk_init_data) { + .name = "hcodec_p1_gate", + .ops = &clk_gate_ops, + .parent_names = (const char *[]){ "hcodec_p1_div" }, + .num_parents = 1, + .flags = CLK_GET_RATE_NOCACHE, + }, +}; + +static struct clk_mux hcodec_mux = { + .reg = (void *)HHI_VDEC3_CLK_CNTL, + .mask = 0x1, + .shift = 31, + .lock = &clk_lock, + .flags = CLK_PARENT_ALTERNATE, + .hw.init = &(struct clk_init_data){ + .name = "hcodec_mux", + .ops = &meson_clk_mux_ops, + .parent_names = (const char *[]){ "hcodec_p0_composite", + "hcodec_p1_composite"}, + .num_parents = 2, + .flags = CLK_GET_RATE_NOCACHE, + }, +}; + +static struct clk_hw *hcodec_clk_hws[] = { + [CLKID_HCODEC_P0_MUX - CLKID_HCODEC_P0_MUX] = &hcodec_p0_mux.hw, + [CLKID_HCODEC_P0_DIV - CLKID_HCODEC_P0_MUX] = &hcodec_p0_div.hw, + [CLKID_HCODEC_P0_GATE - CLKID_HCODEC_P0_MUX] = &hcodec_p0_gate.hw, + [CLKID_HCODEC_P1_MUX - CLKID_HCODEC_P0_MUX] = &hcodec_p1_mux.hw, + [CLKID_HCODEC_P1_DIV - CLKID_HCODEC_P0_MUX] = &hcodec_p1_div.hw, + [CLKID_HCODEC_P1_GATE - CLKID_HCODEC_P0_MUX] = &hcodec_p1_gate.hw, + [CLKID_HCODEC_MUX - CLKID_HCODEC_P0_MUX] = &hcodec_mux.hw, +}; + +/* cts_hevc_clk */ +static struct clk_mux hevc_p0_mux = { + .reg = (void *)HHI_VDEC2_CLK_CNTL, + .mask = 0x7, + .shift = 25, + .lock = &clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "hevc_p0_mux", + .ops = &clk_mux_ops, + .parent_names = g12a_dec_parent_names, + .num_parents = 8, + .flags = CLK_GET_RATE_NOCACHE, + }, +}; + +static struct clk_divider hevc_p0_div = { + .reg = (void *)HHI_VDEC2_CLK_CNTL, + .shift = 16, + .width = 7, + .lock = &clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "hevc_p0_div", + .ops = &clk_divider_ops, + .parent_names = (const char *[]){ "hevc_p0_mux" }, + .num_parents = 1, + .flags = CLK_GET_RATE_NOCACHE, + }, +}; + +static struct clk_gate hevc_p0_gate = { + .reg = (void *)HHI_VDEC2_CLK_CNTL, + .bit_idx = 24, + .lock = &clk_lock, + .hw.init = &(struct clk_init_data) { + .name = "hevc_p0_gate", + .ops = &clk_gate_ops, + .parent_names = (const char *[]){ "hevc_p0_div" }, + .num_parents = 1, + .flags = CLK_GET_RATE_NOCACHE, + }, +}; + +static struct clk_mux hevc_p1_mux = { + .reg = (void *)HHI_VDEC4_CLK_CNTL, + .mask = 0x7, + .shift = 25, + .lock = &clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "hevc_p1_mux", + .ops = &clk_mux_ops, + .parent_names = g12a_dec_parent_names, + .num_parents = 8, + .flags = CLK_GET_RATE_NOCACHE, + }, +}; + +static struct clk_divider hevc_p1_div = { + .reg = (void *)HHI_VDEC4_CLK_CNTL, + .shift = 16, + .width = 7, + .lock = &clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "hevc_p1_div", + .ops = &clk_divider_ops, + .parent_names = (const char *[]){ "hevc_p1_mux" }, + .num_parents = 1, + .flags = CLK_GET_RATE_NOCACHE, + }, +}; + +static struct clk_gate hevc_p1_gate = { + .reg = (void *)HHI_VDEC4_CLK_CNTL, + .bit_idx = 24, + .lock = &clk_lock, + .hw.init = &(struct clk_init_data) { + .name = "hevc_p1_gate", + .ops = &clk_gate_ops, + .parent_names = (const char *[]){ "hevc_p1_div" }, + .num_parents = 1, + .flags = CLK_GET_RATE_NOCACHE, + }, +}; + +static struct clk_mux hevc_mux = { + .reg = (void *)HHI_VDEC4_CLK_CNTL, + .mask = 0x1, + .shift = 31, + .lock = &clk_lock, + .flags = CLK_PARENT_ALTERNATE, + .hw.init = &(struct clk_init_data){ + .name = "hevc_mux", + .ops = &meson_clk_mux_ops, + .parent_names = (const char *[]){ "hevc_p0_composite", + "hevc_p1_composite"}, + .num_parents = 2, + .flags = CLK_GET_RATE_NOCACHE, + }, +}; + +static struct clk_hw *hevc_clk_hws[] = { + [CLKID_HEVC_P0_MUX - CLKID_HEVC_P0_MUX] = &hevc_p0_mux.hw, + [CLKID_HEVC_P0_DIV - CLKID_HEVC_P0_MUX] = &hevc_p0_div.hw, + [CLKID_HEVC_P0_GATE - CLKID_HEVC_P0_MUX] = &hevc_p0_gate.hw, + [CLKID_HEVC_P1_MUX - CLKID_HEVC_P0_MUX] = &hevc_p1_mux.hw, + [CLKID_HEVC_P1_DIV - CLKID_HEVC_P0_MUX] = &hevc_p1_div.hw, + [CLKID_HEVC_P1_GATE - CLKID_HEVC_P0_MUX] = &hevc_p1_gate.hw, + [CLKID_HEVC_MUX - CLKID_HEVC_P0_MUX] = &hevc_mux.hw, +}; + static const char * const vpu_parent_names[] = { "fclk_div3", "fclk_div4", "fclk_div5", "fclk_div7", "null", "null", "null", "null"}; @@ -403,6 +733,33 @@ void meson_g12a_media_init(void) dsi_meas_div.reg = clk_base + (u64)(dsi_meas_div.reg); dsi_meas_gate.reg = clk_base + (u64)(dsi_meas_gate.reg); #endif + /* cts_vdec_clk */ + vdec_p0_mux.reg = clk_base + (u64)(vdec_p0_mux.reg); + vdec_p0_div.reg = clk_base + (u64)(vdec_p0_div.reg); + vdec_p0_gate.reg = clk_base + (u64)(vdec_p0_gate.reg); + vdec_p1_mux.reg = clk_base + (u64)(vdec_p1_mux.reg); + vdec_p1_div.reg = clk_base + (u64)(vdec_p1_div.reg); + vdec_p1_gate.reg = clk_base + (u64)(vdec_p1_gate.reg); + vdec_mux.reg = clk_base + (u64)(vdec_mux.reg); + + /* cts_hcodec_clk */ + hcodec_p0_mux.reg = clk_base + (u64)(hcodec_p0_mux.reg); + hcodec_p0_div.reg = clk_base + (u64)(hcodec_p0_div.reg); + hcodec_p0_gate.reg = clk_base + (u64)(hcodec_p0_gate.reg); + hcodec_p1_mux.reg = clk_base + (u64)(hcodec_p1_mux.reg); + hcodec_p1_div.reg = clk_base + (u64)(hcodec_p1_div.reg); + hcodec_p1_gate.reg = clk_base + (u64)(hcodec_p1_gate.reg); + hcodec_mux.reg = clk_base + (u64)(hcodec_mux.reg); + + /* cts_hevc_clk */ + hevc_p0_mux.reg = clk_base + (u64)(hevc_p0_mux.reg); + hevc_p0_div.reg = clk_base + (u64)(hevc_p0_div.reg); + hevc_p0_gate.reg = clk_base + (u64)(hevc_p0_gate.reg); + hevc_p1_mux.reg = clk_base + (u64)(hevc_p1_mux.reg); + hevc_p1_div.reg = clk_base + (u64)(hevc_p1_div.reg); + hevc_p1_gate.reg = clk_base + (u64)(hevc_p1_gate.reg); + hevc_mux.reg = clk_base + (u64)(hevc_mux.reg); + /* cts_vpu_clk */ vpu_p0_mux.reg = clk_base + (u64)(vpu_p0_mux.reg); vpu_p0_div.reg = clk_base + (u64)(vpu_p0_div.reg); @@ -444,6 +801,106 @@ void meson_g12a_media_init(void) pr_err("%s: %d clk_register_composite dsi_meas_composite error\n", __func__, __LINE__); #endif + + /* cts_vdec_clk */ + clks[CLKID_VDEC_P0_COMP] = clk_register_composite(NULL, + "vdec_p0_composite", + g12a_dec_parent_names, 8, + vdec_clk_hws[CLKID_VDEC_P0_MUX - CLKID_VDEC_P0_MUX], + &clk_mux_ops, + vdec_clk_hws[CLKID_VDEC_P0_DIV - CLKID_VDEC_P0_MUX], + &clk_divider_ops, + vdec_clk_hws[CLKID_VDEC_P0_GATE - CLKID_VDEC_P0_MUX], + &clk_gate_ops, 0); + if (IS_ERR(clks[CLKID_VDEC_P0_COMP])) + panic("%s: %d clk_register_composite vdec_p0_composite error\n", + __func__, __LINE__); + + clks[CLKID_VDEC_P1_COMP] = clk_register_composite(NULL, + "vdec_p1_composite", + g12a_dec_parent_names, 8, + vdec_clk_hws[CLKID_VDEC_P1_MUX - CLKID_VDEC_P0_MUX], + &clk_mux_ops, + vdec_clk_hws[CLKID_VDEC_P1_DIV - CLKID_VDEC_P0_MUX], + &clk_divider_ops, + vdec_clk_hws[CLKID_VDEC_P1_GATE - CLKID_VDEC_P0_MUX], + &clk_gate_ops, 0); + if (IS_ERR(clks[CLKID_VDEC_P1_COMP])) + panic("%s: %d clk_register_composite vdec_p1_composite error\n", + __func__, __LINE__); + + clks[CLKID_VDEC_MUX] = clk_register(NULL, + vdec_clk_hws[CLKID_VDEC_MUX - CLKID_VDEC_P0_MUX]); + if (IS_ERR(clks[CLKID_VDEC_MUX])) + panic("%s: %d clk_register vdec_mux error\n", + __func__, __LINE__); + + /* cts_hcodec_clk */ + clks[CLKID_HCODEC_P0_COMP] = clk_register_composite(NULL, + "hcodec_p0_composite", + g12a_dec_parent_names, 8, + hcodec_clk_hws[CLKID_HCODEC_P0_MUX - CLKID_HCODEC_P0_MUX], + &clk_mux_ops, + hcodec_clk_hws[CLKID_HCODEC_P0_DIV - CLKID_HCODEC_P0_MUX], + &clk_divider_ops, + hcodec_clk_hws[CLKID_HCODEC_P0_GATE - CLKID_HCODEC_P0_MUX], + &clk_gate_ops, 0); + if (IS_ERR(clks[CLKID_HCODEC_P0_COMP])) + panic("%s: %d clk_register_composite hcodec_p0_composite error\n", + __func__, __LINE__); + + clks[CLKID_HCODEC_P1_COMP] = clk_register_composite(NULL, + "hcodec_p1_composite", + g12a_dec_parent_names, 8, + hcodec_clk_hws[CLKID_HCODEC_P1_MUX - CLKID_HCODEC_P0_MUX], + &clk_mux_ops, + hcodec_clk_hws[CLKID_HCODEC_P1_DIV - CLKID_HCODEC_P0_MUX], + &clk_divider_ops, + hcodec_clk_hws[CLKID_HCODEC_P1_GATE - CLKID_HCODEC_P0_MUX], + &clk_gate_ops, 0); + if (IS_ERR(clks[CLKID_HCODEC_P1_COMP])) + panic("%s: %d clk_register_composite hcodec_p1_composite error\n", + __func__, __LINE__); + + clks[CLKID_HCODEC_MUX] = clk_register(NULL, + hcodec_clk_hws[CLKID_HCODEC_MUX - CLKID_HCODEC_P0_MUX]); + if (IS_ERR(clks[CLKID_HCODEC_MUX])) + panic("%s: %d clk_register hcodec_mux error\n", + __func__, __LINE__); + + /* cts_hevc_clk */ + clks[CLKID_HEVC_P0_COMP] = clk_register_composite(NULL, + "hevc_p0_composite", + g12a_dec_parent_names, 8, + hevc_clk_hws[CLKID_HEVC_P0_MUX - CLKID_HEVC_P0_MUX], + &clk_mux_ops, + hevc_clk_hws[CLKID_HEVC_P0_DIV - CLKID_HEVC_P0_MUX], + &clk_divider_ops, + hevc_clk_hws[CLKID_HEVC_P0_GATE - CLKID_HEVC_P0_MUX], + &clk_gate_ops, 0); + if (IS_ERR(clks[CLKID_HEVC_P0_COMP])) + panic("%s: %d clk_register_composite hevc_p0_composite error\n", + __func__, __LINE__); + + clks[CLKID_HEVC_P1_COMP] = clk_register_composite(NULL, + "hevc_p1_composite", + g12a_dec_parent_names, 8, + hevc_clk_hws[CLKID_HEVC_P1_MUX - CLKID_HEVC_P0_MUX], + &clk_mux_ops, + hevc_clk_hws[CLKID_HEVC_P1_DIV - CLKID_HEVC_P0_MUX], + &clk_divider_ops, + hevc_clk_hws[CLKID_HEVC_P1_GATE - CLKID_HEVC_P0_MUX], + &clk_gate_ops, 0); + if (IS_ERR(clks[CLKID_HEVC_P1_COMP])) + panic("%s: %d clk_register_composite hevc_p1_composite error\n", + __func__, __LINE__); + + clks[CLKID_HEVC_MUX] = clk_register(NULL, + hevc_clk_hws[CLKID_HEVC_MUX - CLKID_HEVC_P0_MUX]); + if (IS_ERR(clks[CLKID_HEVC_MUX])) + panic("%s: %d clk_register hevc_mux error\n", + __func__, __LINE__); + /* cts_vpu_clk */ clks[CLKID_VPU_P0_COMP] = clk_register_composite(NULL, "vpu_p0_composite", diff --git a/drivers/amlogic/clk/g12a/g12a_clk_misc.c b/drivers/amlogic/clk/g12a/g12a_clk_misc.c new file mode 100644 index 000000000000..8f01b7ffd6a6 --- /dev/null +++ b/drivers/amlogic/clk/g12a/g12a_clk_misc.c @@ -0,0 +1,80 @@ +/* + * drivers/amlogic/clk/g12a/g12a_clk_misc.c + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "../clkc.h" +#include "g12a.h" + +static const char * const ts_parent_names[] = { "xtal" }; + +static struct clk_divider g12a_ts_clk_div = { + .reg = (void *)HHI_TS_CLK_CNTL, + .shift = 0, + .width = 8, + .lock = &clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "ts_clk_div", + .ops = &clk_divider_ops, + .parent_names = (const char *[]){ "xtal" }, + .num_parents = 1, + .flags = CLK_GET_RATE_NOCACHE, + }, +}; + +static struct clk_gate g12a_ts_clk_gate = { + .reg = (void *)HHI_TS_CLK_CNTL, + .bit_idx = 8, + .lock = &clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "ts_clk_gate", + .ops = &clk_gate_ops, + .parent_names = (const char *[]){ "ts_clk_div" }, + .num_parents = 1, + .flags = CLK_GET_RATE_NOCACHE, + }, +}; + +void meson_g12a_misc_init(void) +{ + /* Populate base address for reg */ + pr_info("%s: register amlogic g12a misc clks\n", __func__); + + g12a_ts_clk_div.reg = clk_base + (u64)(g12a_ts_clk_div.reg); + g12a_ts_clk_gate.reg = clk_base + (u64)(g12a_ts_clk_gate.reg); + + clks[CLKID_TS_COMP] = clk_register_composite(NULL, + "ts_comp", + ts_parent_names, 1, + NULL, + NULL, + &g12a_ts_clk_div.hw, + &clk_divider_ops, + &g12a_ts_clk_gate.hw, + &clk_gate_ops, 0); + if (IS_ERR(clks[CLKID_TS_COMP])) + panic("%s: %d clk_register_composite ts_comp error\n", + __func__, __LINE__); + + pr_info("%s: done.\n", __func__); +} diff --git a/include/dt-bindings/clock/amlogic,g12a-clkc.h b/include/dt-bindings/clock/amlogic,g12a-clkc.h index 4197d3671daf..0c8e07f9e134 100644 --- a/include/dt-bindings/clock/amlogic,g12a-clkc.h +++ b/include/dt-bindings/clock/amlogic,g12a-clkc.h @@ -85,14 +85,14 @@ #define GATE_BASE1 (GATE_BASE0 + 22) #define CLKID_AUDIO (GATE_BASE1 + 0) #define CLKID_ETH_CORE (GATE_BASE1 + 1) -#define CLKID_U_STP_TOP (GATE_BASE1 + 2) +#define CLKID_DEMUX (GATE_BASE1 + 2) #define CLKID_AIFIFO (GATE_BASE1 + 3) #define CLKID_ADC (GATE_BASE1 + 4) #define CLKID_UART1 (GATE_BASE1 + 5) #define CLKID_G2D (GATE_BASE1 + 6) #define CLKID_RESET (GATE_BASE1 + 7) #define CLKID_PCIE_COMB (GATE_BASE1 + 8) -#define CLKID_PARSER (GATE_BASE1 + 9) +#define CLKID_DOS_PARSER (GATE_BASE1 + 9) #define CLKID_USB_GENERAL (GATE_BASE1 + 10) #define CLKID_PCIE_PHY (GATE_BASE1 + 11) #define CLKID_AHB_ARB0 (GATE_BASE1 + 12) @@ -110,7 +110,29 @@ #define CLKID_VPU_INTR (GATE_BASE2 + 8) #define CLKID_GIC (GATE_BASE2 + 9) -#define GATE_AO_BASE (GATE_BASE2 + 10) +/*HHI_GCLK_OTHER: 0x54*/ +#define GATE_BASE3 (GATE_BASE2 + 10) +#define CLKID_VCLK2_VENCI0 (GATE_BASE3 + 0) +#define CLKID_VCLK2_VENCI1 (GATE_BASE3 + 1) +#define CLKID_VCLK2_VENCP0 (GATE_BASE3 + 2) +#define CLKID_VCLK2_VENCP1 (GATE_BASE3 + 3) +#define CLKID_VCLK2_VENCT0 (GATE_BASE3 + 4) +#define CLKID_VCLK2_VENCT1 (GATE_BASE3 + 5) +#define CLKID_VCLK2_OTHER (GATE_BASE3 + 6) +#define CLKID_VCLK2_ENCI (GATE_BASE3 + 7) +#define CLKID_VCLK2_ENCP (GATE_BASE3 + 8) +#define CLKID_DAC_CLK (GATE_BASE3 + 9) +#define CLKID_AOCLK_GATE (GATE_BASE3 + 10) +#define CLKID_IEC958_GATE (GATE_BASE3 + 11) +#define CLKID_ENC480P (GATE_BASE3 + 12) +#define CLKID_RNG1 (GATE_BASE3 + 13) +#define CLKID_VCLK2_ENCT (GATE_BASE3 + 14) +#define CLKID_VCLK2_ENCL (GATE_BASE3 + 15) +#define CLKID_VCLK2_VENCLMMC (GATE_BASE3 + 16) +#define CLKID_VCLK2_VENCL (GATE_BASE3 + 17) +#define CLKID_VCLK2_OTHER1 (GATE_BASE3 + 18) + +#define GATE_AO_BASE (GATE_BASE3 + 19) #define CLKID_AO_MEDIA_CPU (GATE_AO_BASE + 0) #define CLKID_AO_AHB_SRAM (GATE_AO_BASE + 1) #define CLKID_AO_AHB_BUS (GATE_AO_BASE + 2) @@ -172,19 +194,47 @@ #define CLKID_DSI_MEAS_COMP (CLKID_MEDIA_BASE + 22) #define CLKID_VPU_CLKB_TMP_COMP (CLKID_MEDIA_BASE + 23) #define CLKID_VPU_CLKB_COMP (CLKID_MEDIA_BASE + 24) +#define CLKID_VDEC_P0_MUX (CLKID_MEDIA_BASE + 25) +#define CLKID_VDEC_P0_DIV (CLKID_MEDIA_BASE + 26) +#define CLKID_VDEC_P0_GATE (CLKID_MEDIA_BASE + 27) +#define CLKID_VDEC_P0_COMP (CLKID_MEDIA_BASE + 28) +#define CLKID_VDEC_P1_MUX (CLKID_MEDIA_BASE + 29) +#define CLKID_VDEC_P1_DIV (CLKID_MEDIA_BASE + 30) +#define CLKID_VDEC_P1_GATE (CLKID_MEDIA_BASE + 31) +#define CLKID_VDEC_P1_COMP (CLKID_MEDIA_BASE + 32) +#define CLKID_VDEC_MUX (CLKID_MEDIA_BASE + 33) +#define CLKID_HCODEC_P0_MUX (CLKID_MEDIA_BASE + 34) +#define CLKID_HCODEC_P0_DIV (CLKID_MEDIA_BASE + 35) +#define CLKID_HCODEC_P0_GATE (CLKID_MEDIA_BASE + 36) +#define CLKID_HCODEC_P0_COMP (CLKID_MEDIA_BASE + 37) +#define CLKID_HCODEC_P1_MUX (CLKID_MEDIA_BASE + 38) +#define CLKID_HCODEC_P1_DIV (CLKID_MEDIA_BASE + 39) +#define CLKID_HCODEC_P1_GATE (CLKID_MEDIA_BASE + 40) +#define CLKID_HCODEC_P1_COMP (CLKID_MEDIA_BASE + 41) +#define CLKID_HCODEC_MUX (CLKID_MEDIA_BASE + 42) +#define CLKID_HEVC_P0_MUX (CLKID_MEDIA_BASE + 43) +#define CLKID_HEVC_P0_DIV (CLKID_MEDIA_BASE + 44) +#define CLKID_HEVC_P0_GATE (CLKID_MEDIA_BASE + 45) +#define CLKID_HEVC_P0_COMP (CLKID_MEDIA_BASE + 46) +#define CLKID_HEVC_P1_MUX (CLKID_MEDIA_BASE + 47) +#define CLKID_HEVC_P1_DIV (CLKID_MEDIA_BASE + 48) +#define CLKID_HEVC_P1_GATE (CLKID_MEDIA_BASE + 49) +#define CLKID_HEVC_P1_COMP (CLKID_MEDIA_BASE + 50) +#define CLKID_HEVC_MUX (CLKID_MEDIA_BASE + 51) -#define CLKID_MISC_BASE (CLKID_MEDIA_BASE + 25) +#define CLKID_MISC_BASE (CLKID_MEDIA_BASE + 52) #define CLKID_SPICC_MUX (CLKID_MISC_BASE + 0) #define CLKID_SPICC_DIV (CLKID_MISC_BASE + 1) #define CLKID_SPICC_GATE (CLKID_MISC_BASE + 2) #define CLKID_SPICC_COMP (CLKID_MISC_BASE + 3) +#define CLKID_TS_COMP (CLKID_MISC_BASE + 4) -#define CLKID_AO_BASE (CLKID_MISC_BASE + 4) +#define CLKID_AO_BASE (CLKID_MISC_BASE + 5) #define CLKID_AO_CLK81 (CLKID_AO_BASE + 0) #define CLKID_SARADC_MUX (CLKID_AO_BASE + 1) #define CLKID_SARADC_DIV (CLKID_AO_BASE + 2) #define CLKID_SARADC_GATE (CLKID_AO_BASE + 3) -#define NR_CLKS (CLKID_MISC_BASE + 4) +#define NR_CLKS (CLKID_AO_BASE + 4) #endif /* __G12A_CLKC_H */