diff --git a/drivers/clk/rockchip/Kconfig b/drivers/clk/rockchip/Kconfig
index 2322c3f04238..ad828efc6e3e 100644
--- a/drivers/clk/rockchip/Kconfig
+++ b/drivers/clk/rockchip/Kconfig
@@ -20,6 +20,24 @@ config ROCKCHIP_CLK_BOOST
 	help
 	  Say y here to enable clk boost.
 
+config ROCKCHIP_CLK_INV
+	bool "Rockchip Clk Inverter"
+	default y if !CPU_RV1126
+	help
+	  Say y here to enable clk Inverter.
+
+config ROCKCHIP_CLK_PVTM
+	bool "Rockchip Clk Pvtm"
+	default y if !CPU_RV1126
+	help
+	  Say y here to enable clk pvtm.
+
+config ROCKCHIP_DCLK_DIV
+	bool "Rockchip Dclk Divider"
+	default y if !CPU_RV1126
+	help
+	  Say y here to enable dclk divider.
+
 config ROCKCHIP_DDRCLK_SCPI
 	bool "Rockchip DDR Clk SCPI"
 	default y if RK3368_SCPI_PROTOCOL
diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile
index 4e4178af8dba..92a8de59577c 100644
--- a/drivers/clk/rockchip/Makefile
+++ b/drivers/clk/rockchip/Makefile
@@ -7,12 +7,12 @@ obj-y	+= clk.o
 obj-y	+= clk-pll.o
 obj-y	+= clk-cpu.o
 obj-y	+= clk-half-divider.o
-obj-y	+= clk-inverter.o
 obj-y	+= clk-mmc-phase.o
 obj-y	+= clk-muxgrf.o
 obj-y	+= clk-ddr.o
-obj-y	+= clk-pvtm.o
-obj-y	+= clk-dclk-divider.o
+obj-$(CONFIG_ROCKCHIP_CLK_INV)	+= clk-inverter.o
+obj-$(CONFIG_ROCKCHIP_CLK_PVTM)	+= clk-pvtm.o
+obj-$(CONFIG_ROCKCHIP_DCLK_DIV)	+= clk-dclk-divider.o
 obj-$(CONFIG_RESET_CONTROLLER)	+= softrst.o
 
 obj-$(CONFIG_CPU_PX30)		+= clk-px30.o
diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c
index 260c5bd6ffa3..06769a020bc7 100644
--- a/drivers/clk/rockchip/clk.c
+++ b/drivers/clk/rockchip/clk.c
@@ -660,11 +660,13 @@ void __init rockchip_clk_register_branches(
 			);
 			break;
 		case branch_inverter:
+#ifdef CONFIG_ROCKCHIP_CLK_INV
 			clk = rockchip_clk_register_inverter(
 				list->name, list->parent_names,
 				list->num_parents,
 				ctx->reg_base + list->muxdiv_offset,
 				list->div_shift, list->div_flags, &ctx->lock);
+#endif
 			break;
 		case branch_factor:
 			clk = rockchip_clk_register_factor_branch(
@@ -684,6 +686,7 @@ void __init rockchip_clk_register_branches(
 				ctx->reg_base);
 			break;
 		case branch_dclk_divider:
+#ifdef CONFIG_ROCKCHIP_DCLK_DIV
 			clk = rockchip_clk_register_dclk_branch(list->name,
 				list->parent_names, list->num_parents,
 				ctx->reg_base, list->muxdiv_offset, list->mux_shift,
@@ -692,6 +695,7 @@ void __init rockchip_clk_register_branches(
 				list->div_flags, list->div_table,
 				list->gate_offset, list->gate_shift,
 				list->gate_flags, flags, list->max_prate, &ctx->lock);
+#endif
 			break;
 		}